<html><head><style type='text/css'>p { margin: 0; }</style></head><body><div style='font-family: arial,helvetica,sans-serif; font-size: 10pt; color: #000000'>Jordan Fix will present his research seminar/general exam on Thursday May 16 at 10AM in <br>Room 402. The members of his committee are: David August (advisor), David Wentzlaff (ELE), <br>and Andrew Appel. Everyone is invited to attend his talk and those faculty wishing to remain <br>for the oral exam following are welcome to do so. His abstract and reading list follow below.<br>-----------------------------<div style="color:#000;font-weight:normal;font-style:normal;text-decoration:none;font-family:Helvetica,Arial,sans-serif;font-size:12pt;"><div><br></div><div><div>Abstract:</div><div>The emergence of multicore architectures necessitates new techniques such as transactional memory (TM) to gain performance without burdening programmers. This talk presents the first evaluation of a hardware multi-threaded transactional (MTX) memory system and improves upon prior proposed designs. MTX enables more diverse parallelization schemes than traditional TM systems which restrict transactions to a single thread, limiting their applicability. Prior software-based MTX memory systems require extra book keeping threads and instructions to manage speculative memory, imposing more overhead than a hardware-based implementation. The proposed hardware MTX memory system employs new transactional instructions, adds new cache state, and is implemented on top of a snoopy MOESI cache coherence protocol, allowing transactions spanning multiple threads to determine their state by snooping coherence messages.</div><div><br></div><div>Reading List:<br>Textbooks:<br>• J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, San Francisco, CA, 1996<br>• A. W. Appel. Modern Compiler Implementation in ML. Cambridge University Press, 1998<br><br>Papers:<br>• Maurice Herlihy and J. Eliot B. Moss. 1993. Transactional memory: architectural support for lock-free data structures. In Proceedings of the 20th annual international symposium on computer architecture (ISCA '93)</div><div>• S. Gopal, T. Vijaykumar, J. Smith, and G. Sohi. 1998. Speculative Versioning Cache. In Proceedings of the 4th International Symposium on High-Performance Computer Architecture (HPCA '98).</div><div>• Lance Hammond, Vicky Wong, Mike Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, and Kunle Olukotun. 2004. Transactional Memory Coherence and Consistency. In Proceedings of the 31st annual international symposium on Computer architecture (ISCA '04).<br></div><div><div>• Nir Shavit and Dan Touitou. 1995. Software transactional memory. In Proceedings of the fourteenth annual ACM symposium on Principles of distributed computing (PODC '95).</div><div>• Arun Raman, Hanjun Kim, Thomas R. Mason, Thomas B. Jablin, and David I. August. 2010. Speculative parallelization using software multi-threaded transactions. In Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems (ASPLOS XV).<br><div><div>• N. Vachharajani. Intelligent Speculation for Pipelined Multithreading. PhD thesis, Department of Computer Science, Princeton University, Princeton, New Jersey, United States, November 2008.</div></div><div>• J. Greggory Steffan, Christopher B. Colohan, Antonia Zhai, and Todd C. Mowry. 2000. A scalable approach to thread-level speculation. In Proceedings of the 27th annual international symposium on Computer architecture (ISCA '00)<br></div>• María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, and Josep Torrellas. 2005. Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. ACM Transactions on Architecture and Code Optimization (TACO '05).</div><div>• James R. Goodman. 1983. Using cache memory to reduce processor-memory traffic. In Proceedings of the 10th annual international symposium on Computer architecture (ISCA '83). </div></div><div>• P. Sweazey and A. J. Smith. 1986. A class of compatible cache consistency protocols and their support by the IEEE futurebus. In Proceedings of the 13th annual international symposium on Computer architecture (ISCA '86).</div></div><br></div><br></div></body></html>