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<div class="WordSection1"><p class="MsoNormal" align="center" style="text-align:center;text-indent:.5in;text-autospace:none">
<span style="font-family:"Georgia","serif";color:#1F497D"><img width="480" height="160" id="Picture_x0020_1" alt="SeminarLogo.jpg" apple-inline="yes" apple-width="yes" apple-height="yes" src="cid:image001.jpg@01CC834C.F1941A30"><b><o:p></o:p></b></span></p><p class="MsoNormal" style="text-indent:.5in;text-autospace:none"><b><span style="font-family:"Georgia","serif"">Speaker: Matthew Mattina<o:p></o:p></span></b></p><p class="MsoNormal" style="text-indent:.5in;text-autospace:none"><span style="font-family:"Georgia","serif""> Tilera
<o:p></o:p></span></p><p class="MsoNormal" style="margin-left:99.0pt;text-indent:-63.0pt;text-autospace:none">
<b><span style="font-family:"Georgia","serif"">Title: Architecture and Performance of the TILE-Gx72 ManyCore Processor<i><o:p></o:p></i></span></b></p><p class="MsoNormal" style="text-indent:.5in"><b><span style="font-family:"Georgia","serif"">Date: Thursday, September 11, 2014<o:p></o:p></span></b></p><p class="MsoNormal" style="text-indent:.5in"><b><span style="font-family:"Georgia","serif"">Time:
</span></b><span style="font-family:"Georgia","serif"">4:30 p.m.<b> </b></span><b><span style="font-size:10.0pt;font-family:"Georgia","serif""> </span></b><b><span style="font-family:"Georgia","serif""> <o:p></o:p></span></b></p><p class="MsoNormal" style="text-indent:.5in"><b><span style="font-family:"Georgia","serif"">Room:
</span></b><span style="font-family:"Georgia","serif"">E</span><span style="font-family:"Georgia","serif"">-Quad, Room B205<o:p></o:p></span></p><p class="MsoNormal" style="text-indent:.5in"><b><span style="font-family:"Georgia","serif"">Host: Prof. David Wentzlaff<o:p></o:p></span></b></p><p class="MsoNormal" style="text-indent:.5in"><b><span style="font-family:NewCenturySchlbk"> </span></b></p><p class="MsoNormal"><b><span style="font-family:"Georgia","serif"">Abstract: </span>
</b><span style="font-family:"Georgia","serif"">This talk describes the Tilera TILE-Gx processor architecture, discusses the design choices that result in high throughput performance and power-efficiency, and presents performance results on representative applications
for the 72-core TILE-Gx72, the flagship processor in Tilera's TILE-Gx family. This processor family is comprised of a series of high-performance, low-power 64-bit manycore processor SoCs, tightly coupled with high performance packet processing. These highly
integrated processors deliver industry-leading performance and performance-per-watt in the embedded networking, cyber security, and high throughput computing markets. Of particular interest is the iMesh network-on-chip, which scales to 100s of cores and provides
high-speed interconnection of all on-die elements and cache coherence across the chip.<o:p></o:p></span></p><p class="MsoNormal"><span style="font-family:"Georgia","serif""> </span></p><p class="MsoNormal"><b><span style="font-family:"Georgia","serif"">Biography: </span>
</b><span style="font-family:"Georgia","serif"">Mr. Mattina is the Chief Technology Officer at Tilera and is responsible for overall processor strategy and technology. As processor architect at Tilera, he co-led the design of the 64-core TILE-Pro, and the 9-
to 72-core TILE-Gx processor families. Prior to Tilera, Mr. Mattina was with Intel Corporation where he was co-lead architect for the Tukwila Multicore Processor, supervising a team of architects and designers. At Intel, Mr. Mattina invented and designed the
Intel Ring Uncore Architecture, used across Intel's x86 multicore processor designs. This technology won the Intel Achievement Award in 2010. Prior to Intel, he was an architect and circuit design engineer at Digital Equipment Corporation, working on the Alpha
EV7 and EV8 processors. Mr. Mattina also served as Technical Leader at Cisco Systems in the TelePresence Infrastructure Business Unit, where he contributed to the hardware and software design of next-generation high-definition video conferencing products.
He has been granted over 20 patents and has published journal and conference papers relating to CPU design, multicore processors, and cache coherence protocols. Mr. Mattina holds a BS in Computer and Systems Engineering from Rensselaer Polytechnic Institute
and a MS in Electrical Engineering from Princeton University.<o:p></o:p></span></p></div></div></div></blockquote></div><br></body></html>