<html><head><style type='text/css'>p { margin: 0; }</style></head><body><div style='font-family: arial,helvetica,sans-serif; font-size: 12pt; color: #000000'><b><i><span style="font-size:12.0pt;color:#1F497D">Sent on behalf of Prof. Kaushik Sengupta</span></i></b><div style="color:#000;font-weight:normal;font-style:normal;text-decoration:none;font-family:Helvetica,Arial,sans-serif;font-size:12pt;"><div class="WordSection1">
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<img id="Picture_x0020_6" src="cid:image012.png@01CFD97C.C72E0DD0" height="47" width="63"><b><span style="font-size:14.0pt;font-family:"Arial","sans-serif";color:black"> IEEE SSCS Lehigh/Princeton/Columbia Chapters Present</span></b><b><i><span style="font-size:14.0pt;font-family:"Arial","sans-serif";color:#0070C1">
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<p class="MsoNormal" style="text-align:center" align="center"><b><i><span style="font-size:14.0pt;font-family:"Arial","sans-serif";color:#0070C1">Distinguished Lecture Colloquia, October 2014</span></i></b><span style="font-size:12.0pt"></span></p>
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<p class="MsoNormal" style="text-align:center" align="center"><b><span style="font-size:9.0pt;color:black">October 16, 2014, 1:30–2:45 pm</span></b></p>
<p class="MsoNormal" style="text-align:center" align="center"><b><u><span style="font-size:9.0pt;color:black">On-Chip Voltage and Timing Diagnostic Circuits</span></u></b></p>
<p class="MsoNormal" style="text-align:center" align="center"><i><span style="font-size:9.0pt">Frank O’Mahony, Intel</span></i></p>
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<p class="MsoNormal"><b><span style="font-size:9.0pt;color:black">Abstract: </span>
</b><span style="font-size:9.0pt;color:black">This talk introduces a set of practical and powerful techniques and circuits to observe and characterize on-die circuitry. Measuring voltage and timing information on the chip itself alleviates the bandwidth and
noise limitations associated with bringing signals off-chip to be measured. Specific applications of these techniques include measurement and characterization of power supply noise, power delivery impedance, clock skew, phase interpolator linearity, I/O eye
margins, waveform capture, RX voltage noise and hysteresis, and RX clock-data jitter. Because the measurements are fully integrated, the rest of the system can be automatically adapted based on these metrics in a stand-alone manner. Best of all, many of these
techniques leverage existing circuitry and are highly digital.</span></p>
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<p class="MsoNormal" style="text-align:center" align="center"><b><span style="font-size:9.0pt;color:black">October 16, 2014, 3:00–4:15 p.m.</span></b><u><span style="font-size:9.0pt;color:black"></span></u></p>
<p class="MsoNormal" style="text-align:center" align="center"><b><u><span style="font-size:9.0pt;color:black">Millimeter-wave and Terahertz Integrated Circuits in Silicon Technologies: Challenges and Solutions</span></u></b></p>
<p class="MsoNormal" style="text-align:center" align="center"><i><span style="font-size:9.0pt">Prof. Payam Hedari, University of California Irvine</span></i></p>
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<p class="MsoNormal"><b><span style="font-size:9.0pt;color:black">Abstract:</span></b><b><span style="font-size:9.0pt;font-family:"Georgia","serif"">
</span></b><span style="font-size:9.0pt;color:black">The vastly under-utilized spectrum across millimeter-wave (mm-wave) and terahertz (THz) bands has generated great deal of excitement to investigate futuristic systems for 10+ gigabit short-range wireless
as well as wideband sensing/imaging applications. Simply put, the shorter wavelength associated with the mm-wave/THz band is appealing since the physical dimensions of the antenna and associated electronics are reduced in size, making it possible to design
multi-antenna structures to achieve beamforming, spatial diversity and multiplexing.
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<p class="MsoNormal"><span style="font-size:9.0pt;color:black">Owing to aggressive scaling in feature size and device fT/fmax, nanoscale (Bi)CMOS technology potentially enables integration of sophisticated systems at THz frequency range, once only be implemented
in compound III-IV semiconductor technologies.</span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;color:black">This talk will give an overview of recent advances in designing silicon-based integrated circuits will be capable of operating close to the maximum operation limits of silicon-based transistors.
The talk then will discuss in depth about two case studies designed in UCI’s Nanoscale Communication Integrated Circuits (NCIC) Labs; namely, the world’s highest fundamental frequency fully differential transceiver in CMOS at 210 GHz, and the world’s highest
frequency PLL-based Synthesizer in Silicon at 300GHz with a wide tuning range.
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<p class="MsoNormal" style="text-align:center" align="center"><b><span style="font-size:9.0pt;color:black">October 16, 2014, 4:30–5:45 p.m.<u></u></span></b></p>
<p class="MsoNormal" style="text-align:center" align="center"><b><u><span style="font-size:9.0pt;color:black">Low-Power, High-Bandwidth, and Ultra-Small Memory Module Design</span></u></b></p>
<p class="MsoNormal" style="text-align:center" align="center"><i><span style="font-size:9.0pt;color:black">Prof. R. Jacob Baker, University of Nevada, Las Vegas</span></i></p>
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<p class="MsoNormal"><b><span style="font-size:9.0pt;color:black">Abstract:</span></b><span style="font-size:9.0pt;color:black"> This work proposes a novel DRAM module and interconnect architectures in an attempt to improve computing energy use and performance.
A low cost advanced packaging technology is used to propose an 8 die and 32-die memory module. The 32-die memory module measures less than 2 cm3. The size and packaging technique allow the memory module to consume less power than conventional module designs.
A 4 Gb DRAM architecture utilizing 64 data pins is proposed. The DRAM architecture is inline with ITRS roadmaps and can consume 50% less power while increasing bandwidth by 100%. The large number of data pins are supported by a low power capacitive-coupled
interconnect. The receivers developed for the capacitive interface were fabricated in 0.5 μm and 65 nm CMOS technologies. The 0.5 μm design operated at 200 Mbps, used a coupling capacitor of 100 fF, and consumed less than 3 pJ/bit of energy. The 65 nm design
operated at 4 Gbps, used a coupling capacitor of 15 fF, and consumed less than 15 fJ/bit and order of magnitude smaller consumptions than previously reported receiver designs.</span></p>
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<p class="MsoFooter" style="text-align:center" align="center"><span style="font-size:10.0pt">Contact Info: Nagi Naganathan,
</span><a href="mailto:nagisub@gmail.com" target="_blank"><span style="font-size:10.0pt">nagisub@gmail.com</span></a><span style="font-size:10.0pt"> or Kaushik Sengupta,
</span><a href="mailto:kaushiks@princeton.edu" target="_blank"><span style="font-size:10.0pt">kaushiks@princeton.edu</span></a><span style="font-size:10.0pt"></span></p>
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