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<p class="MsoNormal" style="text-align:center" align="center"><span style="font-size:20.0pt">“Instruction Sets Want to Be Free: A Case for RISC-V”</span></p>
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<b>David Patterson, Professor, Electrical Engineering & Computer Science, University of California-Berkeley</b><b><span style="font-size:12.0pt"></span></b></p>
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<b><span style="font-size:12.0pt">Wednesday, November 11, 2015</span></b></p>
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<b><span style="font-size:12.0pt">4:30 – 5:45 pm</span></b></p>
<p class="MsoNormal" style="text-align:center" align="center"><b><i><span style="font-size:12.0pt">Reception to Follow</span></i></b></p>
<p class="MsoNormal" style="text-align:center" align="center"><b><i><span style="font-size:12.0pt">Friend Center, Convocation Room</span></i></b></p>
<p class="Abstract" style="margin-top:0in;text-indent:0in"><span style="font-size:12.0pt;font-family:"Cambria","serif""> </span></p>
<p class="Abstract" style="margin-top:0in;text-indent:0in"><span style="font-size:12.0pt;font-family:"Calibri","sans-serif"">Abstract:</span></p>
<p class="MsoNormal"><span style="font-size:12.0pt;color:black">We start by quickly reviewing 50 years of computer architecture to show there is now widespread agreement on instruction set architecture (ISA). Unlike most other fields, despite this harmony there
is no open alternative to proprietary offerings from ARM and Intel.</span><span style="font-size:12.0pt"></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black">Thus, we propose RISC-V (“RISC Five”), which targets Systems on a Chip (SoC). It has:</span><span style="font-size:12.0pt"></span></p>
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<span style="font-size:12.0pt">A small base of <50 classic RISC instructions that run a full open-source software stack.</span></li><li class="MsoNormal" style="color:black;mso-list:l1 level1 lfo3;vertical-align:baseline">
<span style="font-size:12.0pt">Opcodes reserved for tailoring an SoC to applications.</span></li><li class="MsoNormal" style="color:black;mso-list:l1 level1 lfo3;vertical-align:baseline">
<span style="font-size:12.0pt">Standard instruction extensions optionally included in an SoC.</span></li><li class="MsoNormal" style="color:black;mso-list:l1 level1 lfo3;vertical-align:baseline">
<span style="font-size:12.0pt">Incorporated, as an open ISA, community suggestions
<i>before</i> extensions are finalized.</span></li><li class="MsoNormal" style="color:black;mso-list:l1 level1 lfo3;vertical-align:baseline">
<span style="font-size:12.0pt">A foundation to evolve the RISC-V slowly based solely on technical reasons voted on by members vs. by companies that inflate ISAs rapidly for business as well as technical reasons; ARM and Intel average about 2 new instructions
per month.</span></li><li class="MsoNormal" style="color:black;mso-list:l1 level1 lfo3;vertical-align:baseline">
<span style="font-size:12.0pt">No restrictions: there is no cost, no paperwork, and anyone can use it.</span></li></ul>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black">Attendees will get a 2-page reference card (“green card”), which lists all RISC-V extensions, to contrast this minimal ISA with the 3,600-page x86 manual and the 5,400-page ARMv8 manual.</span><span style="font-size:12.0pt"></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black">We conclude by recapping 10 RISC-V chips built using Agile methods in just 4 years, including how shockingly cheap it is today to manufacture 100 2x2-mm, 28-nm chips. We used Chisel, a new hardware
design language that reduces design effort by greatly increasing reuse.</span><span style="font-size:12.0pt"></span></p>
<p class="Abstract" style="margin-top:0in;text-indent:0in"><span style="font-size:12.0pt;font-family:"Calibri","sans-serif""> </span></p>
<p class="Abstract" style="margin-top:0in;text-indent:0in"><span style="font-size:12.0pt;font-family:"Calibri","sans-serif"">Bio:</span></p>
<p style="margin:0in;margin-bottom:.0001pt"><span style="font-family:"Calibri","sans-serif";color:black">David Patterson joined UC Berkeley nearly 40 years ago. He has been Director of several research labs, Chair of Berkeley’s CS Division, Chair of the Computing
Research Association, and President of ACM. His most successful projects are likely Reduced Instruction Set Computers (RISC), Redundant Arrays of Inexpensive Disks (RAID), and Network of Workstations (NOW), all of which helped lead to multi-billion-dollar
industries. This research led to many papers, 6 books, and about 35 honors for him and his friends, including election to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He shared the
IEEE von Neumann Medal and the NEC C&C Prize with John Hennessy, co-author of two of his books and President of Stanford University.</span></p>
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<p style="margin:0in;margin-bottom:.0001pt"><b><span style="font-family:"Calibri","sans-serif";color:black">Host:</span></b><span style="font-family:"Calibri","sans-serif";color:black"> Ruby Lee, Forrest G. Hamrick Professor in Engineering, Professor of Electrical
Engineering, Department of Electrical Engineering</span><span style="font-family:"Calibri","sans-serif""></span></p>
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<p class="MsoNormal"><i><span style="font-size:8.0pt">This seminar is supported with funds from the Korhammer Lecture Series</span></i></p></div></div></div></body></html>