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<div class="">Yushan Su will present her General Exam on Thursday, October 25, 2018 at 12:30pm in CS 401.</div><div class=""><br data-mce-bogus="1"></div><div class="">The members of her committee are <span style="font-size: 12pt;" data-mce-style="font-size: 12pt;">Kai </span>Li (advisor), Kyle Jamieson, and David August.</div><div class=""><br data-mce-bogus="1"></div><div class="">Everyone is invited to attend her talk, and those faculty wishing to remain for the oral exam following are welcome to do so. Her abstract and reading list follow below.</div><div class=""></div></div></span></div></div><div data-marker="__QUOTED_TEXT__"><div data-marker="__QUOTED_TEXT__"><br></div><div data-marker="__QUOTED_TEXT__">Title:</div><div data-marker="__QUOTED_TEXT__">FPGA Accelerator for 2D Iterative Compressed Sensing Reconstruction<br></div><div data-marker="__QUOTED_TEXT__"><br></div><div data-marker="__QUOTED_TEXT__">Abstract:</div><div data-marker="__QUOTED_TEXT__">During the past decade, Compressed Sensing (CS) has emerged as an important method in signal acquisition and processing, allowing the reconstruction of original data from sparse signals with a significantly lower sampling rate than traditional sampling techniques. Among the CS reconstruction algorithms, iterative algorithms can achieve high accuracy, but require intensive computation. As quite a few applications of CS such as biomedical imaging and radar imaging have real-time constraints, how to accelerate the performance of iterative CS reconstruction algorithms is a challenging problem. In this research, we explore how to build an accelerator of 2D iterative CS reconstruction algorithms for FPGAs, since they can potentially achieve higher performance to power ratio than CPUs and GPUs, and they are more programmable than ASICs. Our approach is based on the methodology to mapping to spatial computing fabrics. We have implemented 2D Iterative Soft-shrinkage Threshold Algorithm (ISTA) on Intel/Altera Stratix 10 FPGA. Comparing with the performance of a CPU and a GPU with similar technologies, the projected performance to power ratio is 24.2x than CPU, 2.4x than GPU running the open-source BART MRI toolkit.</div><div data-marker="__QUOTED_TEXT__"><br></div><div data-marker="__QUOTED_TEXT__"><br></div><div data-marker="__QUOTED_TEXT__">Reading List:</div><div data-marker="__QUOTED_TEXT__">Candès, Emmanuel J., and Michael B. Wakin. "An introduction to compressive sampling." IEEE signal processing magazine 25.2 (2008): 21-30.</div><div data-marker="__QUOTED_TEXT__">Lustig, Michael, David Donoho, and John M. Pauly. "Sparse MRI: The application of compressed sensing for rapid MR imaging." Magnetic Resonance in Medicine: An Official Journal of the International Society for Magnetic Resonance in Medicine 58.6 (2007): 1182-1195.</div><div data-marker="__QUOTED_TEXT__">Compton, Katherine, and Scott Hauck. "Reconfigurable computing: a survey of systems and software." ACM Computing Surveys (csuR) 34.2 (2002): 171-210.</div><div data-marker="__QUOTED_TEXT__">Parashar, Angshuman, et al. "Triggered instructions: a control paradigm for spatially-programmed architectures." ACM SIGARCH Computer Architecture News. Vol. 41. No. 3. ACM, 2013.</div><div data-marker="__QUOTED_TEXT__">Lee, Edward A., and David G. Messerschmitt. "Synchronous data flow." Proceedings of the IEEE 75.9 (1987): 1235-1245.</div><div data-marker="__QUOTED_TEXT__">Chen, Ren, Hoang Le, and Viktor K. Prasanna. "Energy efficient parameterized FFT architecture." Field Programmable Logic and Applications (FPL), 2013 23rd International Conference on. IEEE, 2013.</div><div data-marker="__QUOTED_TEXT__">Zeng, Hanqing, et al. "A framework for generating high throughput CNN implementations on FPGAs." Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, 2018.</div><div data-marker="__QUOTED_TEXT__">Bai, Lin, et al. "High-speed compressed sensing reconstruction on FPGA using OMP and AMP." Electronics, Circuits and Systems (ICECS), 19th IEEE International Conference on. 2012.</div><div data-marker="__QUOTED_TEXT__">Stanislaus, Jerome LVM, and Tinoosh Mohsenin. "Low-complexity FPGA implementation of compressive sensing reconstruction." Computing, Networking and Communications (ICNC), 2013 International Conference on. IEEE, 2013.</div><div data-marker="__QUOTED_TEXT__">Quan, Yinghui, et al. "FPGA implementation of real-time compressive sensing with partial Fourier dictionary." International Journal of Antennas and Propagation 2016 (2016).</div><div data-marker="__QUOTED_TEXT__"><br></div><div data-marker="__QUOTED_TEXT__"><br data-mce-bogus="1"></div><div data-marker="__QUOTED_TEXT__">Book List:</div><div data-marker="__QUOTED_TEXT__">Hennessy, John L., and David A. Patterson. Computer architecture: a quantitative approach. Elsevier, 2011.</div><div data-marker="__QUOTED_TEXT__">Cormen, Thomas H., et al. Introduction to algorithms. MIT press, 2009.</div><div><br></div></div></div></body></html>