January 2002 - ixp1200 - lists.cs.princeton.edu

RE: [ixp1200] Cost of developping with KEIXP12EBAB
by Brandewie, Dirk J 11 Mar '02

11 Mar '02

Hi Loren, > Will the KEIXP12EBAB kits (which I am told include C0 Silicon) run ARM > Linux out of the box? (The SDK 2.0 documentation centers around the > development platform with the WinNT SBC, but states that you > dont need to > use the WinNT SBC, if you have your own workstation. This > seems to imply > that I should not have any trouble loading Linux on the evaluation kit > too, so long as I have a WinNT workstation.) The KEIXP12EBAB kits will run Linux out of the box you can find the distribution at ftp://ftp.netwinder.org/users/u/urnaik/. Be aware that SDK 2.0 does not support KEIXP12EBAB. All the tools may be used to develop code but the micro-ace infrastructure will not run. > > Does anyone know how much Intel wants for the Microengine C Compiler? > We are in the process of arranging special education pricing but don't have a final answer yet stay tuned. > What other tools are required that I don't know about? Not a required tool but another environment that runs on the eval system is available at http://www.cs.princeton.edu/nsg/vera/ > > Can you develop on the evaluation kit using only free software tools? Yes you can do all your development with the tools from the SDK and the GCC that is part of the Linux distribution. --Dirk

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Evaluation of Vera
by Tan Chee Wei 31 Jan '02

31 Jan '02

Hallo, There are a couple of problems and questions which I have while evaluating Vera's software and reading the Princeton papers. I appreciate advice. 1)I tested the software sgo on several machines. One persistent problem is that "sgo X.srec" could only execute once. The subsequent execution would lead to segmentation fault of sgo and the machine would normally freeze. If "sgo X.srec" is used, I got the following errors: +++runIXP1200:signal=0xffffffff expecting entry address(0xC1002000) +++IXP1200 is not a mem target on pri PCI and ...not a bus master on pri PCI. If "sgo -r X.srec" is used, more errors pop up: +++Unable to handle kernel NULL pointer dereference at virtual address 00000000 +++printing eip:00000000 +++*pde:00000000 +++Oops:00000000 +++CPU:0 +++EIP:0010:{<00000000>} +++Eflags:00010097 +++eax ffffe0c ebx:00027396 ecx:c02bb54e0 edx:0x1d +++esi:d1bfc960 edi:0x5622 ebp:c5479b38 esp:c5479b10 +++Process sgo (pid:1497, stackpage=c5479000) +++Call Trace.... +++Bad EIP +++hda:lost interrupt I tried resetting the board first, like using the minicom reset as well as the reset pins on the ixp before repeating the above commands. But I still have the same segmentation fault and bad EIP problem. 2)How does one create the vth0,.... device interface on Pentium as described in the paper ? Will the forwarder's admission control that runs on Pentium be included in future release ? 3)Say, I have a simple receiver and sender set-up 10.60.0.38--->[Port 1]Vera[Port 0]--->192.168.133.147 My routing cache's content is : {"10.60.0.38", "192.168.133.147", "00:80:C7:F6:3A:BB", "00:E0:29:00:8C:AE",0x00} "192.168.133.147", "10.60.0.38", "00:E0:29:00:8C:AE", "00:80:C7:F6:3A:BB",0x01} It seems that my ping packets got forwarded but the acknowledgement did not come back. Then, I used a traffic generator and it could be observed that IP packets get forwarded by IXP1200 as normal but did not get transmitted out of the port. The uengines were polling the sa queue. For each packet, they did the ipmm_packet_read:Reading 64 (out of 64) bytes...at say address 0x00284400 and ended with ipmm_packet_write to the same address 0x00284400. Also, packets could only be transmitted out at port 0 using the command keys at the minicom but not port 1. how could I make my ping work ? 4) Each port has 16 queues. How are they organized ? ie. starting from which address ? Thank You very much and kind regards, cheewei

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MPLS implementation on VERA...
by Qiu Qiang 29 Jan '02

29 Jan '02

Dear All, Currently we are trying to build a router with MPLS integrated using ixp1200 network processor. We would like to enhance the currentVera software with MPLS implementation. Suggestion will be appreciated on the following several issues: 1.) How to implement/load a MPLS forwarder 2.) How to implement a efficient MPLS labeling method 3.) How/Where to insert the MPLS header to packet 4.) What is the best way to balance the work among the three processor hierarchy. Any other issues on MPLS implementation on VERA are welcome to be raised. By the way, is there any existing VERA work on MPLS ? Best Regards, Qiu Qiang

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RE: [ixp1200] Re: Some queries on VERA and the IXP1200EB in gener al.
by Tan Chee Wei 25 Jan '02

25 Jan '02

Dear Poh Kit, >What's the difference between setting up the system with libixprouter >and VERA and plugging it into the PCI slot of a motherboard with a host >processor and just flashing the boot ROM with Cygmon and booting a Linux >kernel image on the original Intel chassis as shown at >http://www.netwinder.org/~urnaik/ixp1200_howto.html ? The main difference is that Princeton's Vera allows a programmer to have more computing power at his disposal if said, one is using the PC+SA+UE configuration. Note that Vera, being a multi-processors design, does not restrict itself to PC+SA+UE configuration. In the IXP1200 hardware reference manual Pg.31,2.7.1, Intel suggests that the SA core may be used in different ways, depending on the application. If the system contains a higher end processor like Pentium, SA can leave system maintenance to Pentium and runs a mini-kernel whilst the Pentium and IXP1200 communicate via PCI bus. Vera accomplishes exactly that. In design where no host processor like Pentium is available such as that described in netwinder, SA is seen as the main processor and runs an RTOS. Vera's router infrastructure and the router in Intel reference designs use different data structures. In short, we have 2 different routers using the IXP1200 board. >Also, are there any archives of the IXP1200 mailing list which I can go >through. This would give me a clearer view of the picture much faster >and maybe avoid asking questions which may have already been asked before.:) do "index ixp1200" to retrieve the archive. do "get ixp1200 filename" to get the specified file in the archive. kind regards, cheewei

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Re: Some queries on VERA and the IXP1200EB in general.
by Scott C. Karlin 24 Jan '02

24 Jan '02

On Thu, Jan 24, 2002 at 12:12:41PM +0800, Chong Poh Kit wrote: > > ... I have some > questions regarding the VERA software from Princeton and also the > IXP12EB (revision B) in general... > > The IXP12EB (Rev. B) that was supplied by Intel currently boots > either VxWorks or Angel/UCOS. Currently, we're booting the hardware > with the VxWorks_Gig binary image found in the IXP SDK 1.3. My > university does not have the Tornado IDE for VxWorks or the VxWorks > RTOS itself. Are these software absolutely necessary for me if I'm > using the VxWorks OS? Yes, I believe so. > If I use the libixprouter package with the VERA software on the > IX12EB, would that be like substituting VxWorks and Tornado with > Linux and VERA? Yes. > What's the difference between developing microcodes for the > stand-alone IXP12EB with the original Intel VxWorks image and the > IX12EB with VERA? Because the StrongARM would be running libixprouter, the interface between the microengines and the StrongARM will be different. > Will it work with microcodes compiled on the IXP SDK ver. 2.0 Linux > Edition? In general, no. I think an analogy would be writing x86 assembly language for Windows and for Linux. The code runs on the same processor and some subroutines would port with no changes; however, code which interfaces with the OS (the StrongARM) would have to change. > I hope you can help answer some of my questions or direct me to > some resources which maybe of some help. The ixp1200 mailing list is a good place to start for ixp1200/VERA questions. Scott

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Using Intel's microcode assembler on Linux
by Yitzchak M. Gottlieb 23 Jan '02

23 Jan '02

It seems that Intel's microcode assembler (v 1.2.76) for the IXP1200 runs under WINE, a Windows compatability layer for Linux. This allows the entire VERA/Libixprouter toolchains to run under Linux. See http://www.winehq.com/ for more information about WINE. Once you have WINE running you can make the following changes in the Libixprouter/ue/src/Makefile: Replace line 43: < AS = $(TOOLSDIR)/uca with: > AS = > # Uncomment the following line to compile under WINE > AS += wine -- > AS += $(TOOLSDIR)/uca This change will be in the upcoming release of Libixprouter which should be available fairly soon. Zuki -- Yitzchak Gottlieb zuki(a)CS.Princeton.EDU

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[ixp1200]subscription
by Jin W. Lee 22 Jan '02

22 Jan '02

subscribe ixp1200

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SRAM Memory Lookup
by S Murali 21 Jan '02

21 Jan '02

Hello, I would like to know how many CYCLES a microengine takes to do a single SRAM memory lookup ? Is it a constant or does it depend on anything ? How does it differ from SDRAM ? Thanks, -Murali

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IXF1002 network statistic registers
by john_zhou＠nai.com 21 Jan '02

21 Jan '02

Hi, Does anyone know how to write program to access to the control registers and network statistic registers of IXF1002 in a intel ixp1200 evaluation board? I noticed there is a directory ixp1200\SA1_CoreLibs\GigaMac_GC82547EB in my installed IXP1200 SDK 2.0, and there should be some APIs there to deal with the IXF1002 registers' accessing. But after I read the source code, I still haven't found any real code to read or write IXF1002's registers. Thanks John

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RE: [ixp1200] SRAM Memory Lookup
by Kalkunte, Suresh S 21 Jan '02

21 Jan '02

Murali, How many microengines contend, how often and what kind of memory accesses (ordered/optimized etc. SRAM/SDRAM) will determine the latencies. To get a ball-park idea of how latencies are affected by the application being executed on the IXP1200, the link to this paper among others might give you some answers <http://www.cs.princeton.edu/nsg/papers/ixp-sosp.html> Suresh -----Original Message----- From: S Murali [mailto:tulasi@csa.iisc.ernet.in] Sent: Sunday, January 20, 2002 11:46 AM To: ixp1200(a)CS.Princeton.EDU Subject: [ixp1200] SRAM Memory Lookup Hello, I would like to know how many CYCLES a microengine takes to do a single SRAM memory lookup ? Is it a constant or does it depend on anything ? How does it differ from SDRAM ? Thanks, -Murali

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