October 2002 - ixp1200 - lists.cs.princeton.edu

Problem running IXP1200 VERA apps
by Magesh Kannan 20 Dec '02

20 Dec '02

Hi, Thanks to some help from this group, I managed to build the IXP1200 applications for Vera. I also built and ran the Hello World test program. Now I have a problem running the IPmm and PktGen applications. When I invoke 'sgo ipmm.srec', the output on the board's serial port stops abruptly. Here is the output. =============================== Jumping to: 0xC1002000 bss_start = 0xC10121A8 bss_end = 0xC1012A40 (length) = 0x00000898 Sbrk_heap_ptr_ = 0xC1013000 Sbrk_heap_end_ = 0xC1CF8000 (length) = 0x00CE5000 (13204 Kbytes) Enabling MMU MMU enabled Calling sram_init() Calling scratch_init() Calling PCI_mapout_init() PCI_mapout_init: PCI_dram_siz = 0x02000000 PCI_mapout_init: PCI_dram_bar = 0xF6000000 Calling my_main() Starting uEngines and control program. --- Control_SystemStart --- Contr ========================== This happens irrespective of if I build the microcode with or without VRP. The LED displays 0x25. The same happens with the application PktGen. What have I done wrong here? Thanks, Magesh

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princeton roms on a rev Bixp1200 Eth. Eval. Board.
by Andrew Moore 18 Nov '02

18 Nov '02

Hi, I've been attempting to get VERA up on a board with rev B arm core (at least its what I had always thought was a REV B - this may be the problem) Possibly there are many more versions of the IXP1200 Ethernet Evaluation Board than I realised and I may be stuck with one that will never fly... I've been following the "update the flash" instructions (http://www.cs.princeton.edu/nsg/vera/README.flash.txt) However everything is fine until futil, Instead of getting C:\>FUtil -c 1 -n -a 0 -o 0 -e 200000 -f FILE.bin Flash Utility, Version 1.2.76 FlashUtil, Version 1.2.76 CPU Revision: 6901C123 Flash Width: 32 Flash Bank Size: 2048 KBytes Flash Type Bank[0]: 28F800B3-B Flash Type Bank[1]: 28F160B3-T Flash Type Bank[2]: 28F160B3-T Flash Type Bank[3]: 28F160B3-T Sending data to remote system... Percent complete: 100 Updating flash... Percent Complete: 100 done I get C:\> FUtil -c 1 -n -a 0 -o 0 -e 200000 -f flashImage.bin Flash Utility, Version 2.01.112 FlashUtil, Version 1.1.109 CPU Revision: 6901C121 Flash Width: 32 Flash Bank Size: 2048 KBytes Flash Type Bank[0]: 28F800B3-B Flash Type Bank[1]: 28F160B3-T Flash Type Bank[2]: Unknown Flash Type Bank[3]: Unknown Sending data to remote system... Percent complete: 100 Error in doing inflate: 'Error FFFFFFFD C:\> Clearly this board doesn't have 2Mb of flash, or its not in the configuration expected. I've tried the same process on other IXP ether Eval boards and it works, but not this particular type. Details: the boards I have that work call themselves Rev C the board has the identifier A13033-001 A02 L1 (this is from the sth/wst corner of the board) (near serial port) the board that gives the error above identifies itself as a Rev B and has the identifier A13033-002 Is this board a waste of time??? Thanks for your thoughts, Andrew. Andrew Moore, Computer Laboratory, University of Cambridge, Ph: +44-1223-763446 Fax: +44-1223-334678 andrew.moore(a)cl.cam.ac.uk www.cl.cam.ac.uk/users/awm22/

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(no subject)
by Rayashish＠aol.com 30 Oct '02

30 Oct '02

Hi all, Hi all, Can somebody help me how to install ixp1200 card in the pci slot linux 7.2 PC i.e. procedure for bringing up the card in the PCI slot and also for downloading over the linux image on it. And where can i find Intel provided PCI drivers and PCI network drivers both on the IXP1200 and the linux host which make the PCI look like ethN interface to the respective linux kernels. Thanks for any help you can offer. --Ashish

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L2 bridging sample microC code
by Fei Chen 29 Oct '02

29 Oct '02

-- Hi, Can any one tell where I can find some L2 bridging sample microC code? I have trouble debugging the transmit module of my code, and a successful experience is really helpful for me! BTW, I'm using ix12eb evaluation board. Thank you very much! Fei

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linux kernel on active plane
by Rayashish＠aol.com 29 Oct '02

29 Oct '02

Hi all, Does anyone have an idea How to port Linux Kernel to IXP1200eb when it runs on active plane ( linux box PCI bus). I am running VERA flash on C0 ev Board. I am trying to run some Workbench compiled program (i.e. file.uof ) on ixp12eb with VERA active plane setting. --Ashish

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RE: [ixp1200] top
by Panesar, Kiran S 29 Oct '02

29 Oct '02

On a similar note, does anyone have "top" running on IXP1200? I was able to cross-compile top using the IXA SDK 2.0, but then top needs libncurses. Also, by the way, ps does not show process priorities. Anyone know why this is so? Kiran -----Original Message----- From: Austen McDonald [mailto:austen@cc.gatech.edu] Sent: Tuesday, October 29, 2002 3:10 AM To: ixp1200(a)CS.Princeton.EDU Subject: Re: [ixp1200] tcpdump Oh, one more thing: of course, my version of tcpdump isnt for grabbing packets off the ports; its for getting packets from the ethernet interface attached to the SA. I dont know if this was what you were looking for or not... > Hi, > I am trying to get some of the traffic monitoring tools. Does anyone > have tcpdump or iptraf for IXP1200? > Thanks, > Chris > >

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Question about Transactor
by xtan＠mail 23 Oct '02

23 Oct '02

Hello! I have encountered some problems on debugging C source code under the Workbench. I want to 'examine' or 'deposit' the C defined variable in transator's command output window. For instance, ex f0.reg.reg_name_0 While the compiler won't generate the symbol representing the variable, I can only use the following instead: ex f0.reg.@b31 We know that the C compiler provide global_label function to preserve the C label. Is there any similar solution to the variable?! Thanks a lot. And thanks for your attention.

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MicroEngine cycles
by Srivatsan S 22 Oct '02

22 Oct '02

Hi, How to calculate the no. of uEngine cycles required for a particular operation (packet reception, header verification and table lookup)? Its very difficult to interpret the same with the statistics provided by the History window in the transactor. Am I missing something? Any help is appreciated. Thanks, Srivatsan ---------------------------------------------------------- Srivatsan S MindTree Consulting, Bangalore. Ph: 91-80-6711777 Extn:1428 ----------------------------------------------------------

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IXF440 10/100 Ethernet controller Issues
by Tan Chee-Wei 17 Oct '02

17 Oct '02

Dear all, Can anyone from Intel advise me on this: The IXF440 Datasheet dated from 1998 to the recent copy makes a reference to the register TERR_STT. (check TERR_STT on Page 34 and 50.) But I think this register cannot be found. I want to know whether TERR_STT is a typo error and what actually is meant is TXMT_STT (register that handles the causes for transmit stops) instead ? Can I also check whether the memory map for Slow ports (MAC 0 and 1) for both Evaluation board and Spectacle Island remains the same, as indicated in the mail "First Pass at Mac Address Map" found in the SDK CDROM: ie. it ranges from base 3840 0000 to base 3840 F000 ? For example 3840 3000 would mean Port 3. However, using OctalMAC_NetStat dump on Spectacle Island, I observed that the status for port 3 were gathered from 3840 3800 instead and not from 3840 3000. I tried to verify by dumping memory from StrongARM and the strange thing is memory portion at 3840 3000 had the corresponding data that I wanted but memory values at 3840 3800 were mostly zeroed. I also noticed that the MAC register TX_TSHD_BOFF was configured to be 0xa3 by NetAPP just before Developer Workbench was run to start the microengines but the moment after the microengines were started and running, TX_TSHD_BOFF changed to 0xaf (FIFO threshold increases dramatically). Shouldn't this threshold be fixed at the start by StrongARM and why should the FIFO threshold change only after microengines start to run? I also tried to read the Slow port portions that are memory mapped to Microengines' SRAM memory address space from 007f ffff to 0070 0000. From the programmer's manual, I know that the microengines can do so but it seems that I cannot read values in SRAM 007f ffff to 0070 0000 using memory watch in the Developer Workbench 2.1 for example sram[0x70182a]. Workbench reported undefined address. However the strange thing is that it read nicely from 0000 0000 to 001f ffff. May I know if there is something I can do to make the Workbench to read that address space ? I appreciate you reading through these questions. Thank You very much. Best regards, cheewei

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MicroC development.
by Jorge Hermosillo G 08 Oct '02

08 Oct '02

Hi all, We are trying to run the examples from the IXP1200 Programming book (not using the ACE framework and debugging from the WorkBench) in the enp2505 board. They are working well in simulation mode, but once we indicate to run them in hardware, the rcv_rdy_lo register is always 0x00 even we are sending packets to the port 0. What do we need to activate the ports? We can see only the Hardware->Options->Ports tab to start them, is there something more we have to do? Thanks Jorge H

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