October 2003 - ixp1200 - lists.cs.princeton.edu

compilation error
by Banit Agrawal 31 Oct '03

31 Oct '03

Hi, I am using IXP1200 Developer WorkBench to compile one of my program. But I got one strange error in compilation. The error is something like this: (0): error : please report to Intel (IP=0x007bf12a, addr=0x00c9d000) Has anyone got this error before? I am gussing that it may be due to lack of code-store space or lack of number of registers. Any pointers in this direction would be helpful. Thanks, Banit - ================================================================== Banit Agrawal Graduate Student Researcher Department of Computer Science (909)-787-2001 UC, Riverside bagrawal(a)cs.ucr.edu CA, 92521 http://www.cs.ucr.edu/~bagrawal ==================================================================

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hot swapping of microcode on IXP1200 microengines
by Sanjay Kumar 31 Oct '03

31 Oct '03

Hi, I am trying to implement an API using which I will be able to load microcode on a particular microengine without disturbing any other microengine (ue) of IXP1200. For this I need to build a microcode object file (.uof) which has code for only one ue. I generate the .uof file only for one microengine as following (e.g. for microengine 2). (dbg.list contain code for only for ue #2) $(UCLD) -u 2 dbg.list -o dbg.uof I have searched the Intel documents and I have not seen a single example where we generate a .uof file for only one ue. everywhere we generate a .uof file which contains code for all the ue's. So I am not sure if the above method will work (though it does generate the dbg.uof file all right). Has anyone tried this method before or something similar in which you generate a .uof file for only one ue? Is it possible to do this? If the answer is yes, has anyone tried to implement this hot swaping of microcode on one microengine without disturbing any other microengine? Thanks for any help, regards, Sanjay

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Question about packet generation program
by 조준우 31 Oct '03

31 Oct '03

I have analyzed and modified PktGen application of VERA project. But I am something confused. In that program, packet is actually transferred? I think that header information of simple packet which is made at PktGen application is not enough. Namely, IP address is just 10.0.0.1 and MAC address is just 00:00:00:01. If I want to transfer packet to real system(ex. another linux PC), I would change these adresses? Plz give me answer or any hints. Thanks!

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More about Packet Generator...
by Bracha Hod 30 Oct '03

30 Oct '03

First, things work perfect before I stop the transmit. I tried to stop the transmit in some ports by giving "skip assignments" to the ports via the transmit scheduler. When I stop the transmit, the receive also stops in those ports. My purpose is to give some ports more bandwidth than other, so by stopping them for a while, the Transmit State Machine skip them and send packets from other ports. I use the original L3fwd16_RFC1812 and only change the part of the transmit scheduler in the file ixp_tx.c. I don't touch in any receive file. The situation of stop receiving packets occure also when I drop the receive packets and don't enqueue them. Thank again Abhijeet. ----- Original Message ----- From: "Abhijeet Joglekar" <abhijeet(a)cs.utah.edu> To: <ixp1200(a)CS.Princeton.EDU> Sent: Thursday, October 30, 2003 1:50 PM Subject: Re: [ixp1200] Packet Generator > > A few questions: > > Do things work fine before you stop transmit? Do packets get forwarded? > Also, why do you need to stop transmit and how do you do it? > > I think you will have to explain a lot more about your setup , and > what exactly are you trying, so that somebody on this list can help. >

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Re: [ixp1200] Packet Generator
by Bracha Hod 30 Oct '03

30 Oct '03

Thanks again. I meant that when I stop transmit, the IX bus device status shows no packet been received . I didn't stop it after "n" packets are received, so if you say that the transmitted packets are not cycled back as the recieve packets, what could be the reason to this situation? ----- Original Message ----- From: "Abhijeet Joglekar" <abhijeet(a)cs.utah.edu> To: <ixp1200(a)CS.Princeton.EDU> Sent: Thursday, October 30, 2003 11:52 AM Subject: Re: [ixp1200] Packet Generator > > > I'll try to explain my second question. > > When I ran the simulator, I've noticed that in case that the transmit > > doesn't works ( I stop to send packets from some reason) the receive also > > stops. > > What do you mean by "receive stops"? Does the simulator give an error > and stop, or the IX bus device status shows no packet been received ? > > Packets should be received at the port continously, unless you have > specifically selected that packet reception should be stopped after > some "n" packets are received. Ofcourse, the ingress microcode might > drop those packets, if there arent enough buffers or if transmit is > not releasing buffers. > > > I assume that in the beginning of the simulation the receiving packets are > > created by the script command, and then the transmitted packets go back as > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >a received packets. > ~~~~~~~~~~~~~~~~~~~~~ > > My question is: if there is some way that the received packets won't be > > the > > transmitted packets, > > so in case I stop transmitting, the receiving continue. > > The transmitted packets are not cycled back as the recieve packets, if > that is what you are asking. > > For instance, you can turn off Egress completely, and in ingress code, > simply count packets and then drop them and release the buffer handle > Packet reception should still work. > > -- abhijeet > >

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Re: [ixp1200] Packet Generator
by Bracha Hod 30 Oct '03

30 Oct '03

Thanks for your reply. I'll try to explain my second question. When I ran the simulator, I've noticed that in case that the transmit doesn't works ( I stop to send packets from some reason) the receive also stops. I assume that in the beginning of the simulation the receiving packets are created by the script command, and then the transmitted packets go back as a received packets. My question is: if there is some way that the received packets won't be the transmitted packets, so in case I stop transmitting, the receiving continue. I hope that now the question is more clear. Thanks! ----- Original Message ----- From: "Abhijeet Joglekar" <abhijeet(a)cs.utah.edu> To: <ixp1200(a)CS.Princeton.EDU> Sent: Thursday, October 30, 2003 10:48 AM Subject: Re: [ixp1200] Packet Generator > > > I'm working of L3fwd16_RFC1812. > > I would like to check my program with packets in different sizes > > (random if possible) > > > > Is any of you can explain me how can I do that? or maybe you have more > > complicate packet generator that you can send me? > > If you are running your application on the simulator, then the Workbench > allows you to create a packet stream with different frame sizes and choose > a random option. Check out the IXP1200 Developer Tool Users Guide in the > Intel documentation. > > > > Another question - How do I change the dependency of the receive and > > transmit in the project ? > > (I want the the receive microengines will send > > packets all the time, without depend in the transmit rate) > > > > Can you rephrase this question? I am not sure I understood it. > > -- abhijeet > > >

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Packet Generator
by Bracha Hod 30 Oct '03

30 Oct '03

Hi, I'm working of L3fwd16_RFC1812. I would like to check my program with packets in different sizes (random if possible) Is any of you can explain me how can I do that? or maybe you have more complicate packet generator that you can send me? Another question - How do I change the dependency of the receive and transmit in the project ? (I want the the receive microengines will send packets all the time, without depend in the transmit rate) Thanks a lot!!

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Clock cycles
by basavaraj_m＠dacafe.com 29 Oct '03

29 Oct '03

Hi, I have question: IX bus speed:66Mhz Core clock freq:166Mhz To check the receive ready flag(rcv_rdy_lo) it requires 11cycles. Details: Queue: 4 cycles Dequeue: 1 cycle Finish and sends signal to thread : 2 cycles thread receives the completion signal: 4 cycles cycles based on core clock frequency My question is: Is their a way to find the cycle counts(for each step) without actually running the code? Thanks, Basu ----------------------------------------- This email was sent using DACafeMail. Get Your FREE 25 MB eMail Account Now. http://cafemail.dcccafe.com

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When is LED of Ethernet turned on?
by 조준우 28 Oct '03

28 Oct '03

Hello. I have gotten many informations from VERA project source and this mailing list-source. Thanks! I have one Question. When is LED of Etherenet turned on? I think that after 'Eth_InitPort(i)', 'Eth_StartPort(i)' function is called, LEDs are turned on. But those are not turned on! What is problem? Broken? LEDs are turned on at any other time? Plz, answer. Thanks.

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Re: [ixp1200] Accessing logical interface information.
by Shyamal Pandya 24 Oct '03

24 Oct '03

>>2. In the StrongARM code, do I have to use crosscalls to get this >>information from the ingressACE, or is there another way? If no other >>way, is there an example I could look at on how to use the crosscall? > >you might look up the ixsys.config file from the strongarm code, but it is >probably better to use crosscalls. Don't know about examples, but the SDK >reference docs will help. Also look at the ixconfig source, because it sets up the ip addresses etc. for all ports as part of Ingress consfiguration. _________________________________________________________________ Enjoy MSN 8 patented spam control and more with MSN 8 Dial-up Internet Service. Try it FREE for one month! http://join.msn.com/?page=dept/dialup

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