May 2003 - ixp1200 - lists.cs.princeton.edu

Question on enp-2505
by Feng Tang 09 Sep '03

09 Sep '03

Hello, Currently, my problem when trying to boot linux is: After the board entered cygmon, I typed "go" command, then the minicom screen show below information: ****************** cygmon>go cygmon_handle_exception()monitor_loop return=0 Returned from breakpoint Waiting for host based download Press space bar to abort host download mode.... .. .. .. Press space bar to abort host download mode.... ******************** Then I open another terminal and entered the directory of /opt/ixasdk/enp-2505/bin. I run the script .create_environment.rc and boot_bv. The screen of boot_bv show: ********************* eht1: unknow interface: No such device rmmod: module pciDgNet is not loaded rmmod: module pciDg is not loaded Booting board before = 0x7e6c6700 ********************* Then the screen of minicom show below information: ******************** Booting linux.... Hit breakpointDisassembling 0xc4e9.8944 mrcge 13, 4, r9, cr3, cr14, {4} Waiting for host based download Press space bar to abort host download mode... Press space bar to abort host download mode... ..

4 7

Re: [ixp1200] Compiling armtoolchain
by rasit＠cs.umanitoba.ca 23 Jul '03

23 Jul '03

Hi David, Moh'd is my student, so I can reply in behalf of him. Actually, unless 3 disk RH9 distribution is missing some package, your suggestion is not valid, as we installed *everything* on the host system, i.e., all packages on all 3 discs. As for the command *before* the failure, the whole package is build by a single make, so we don't know unless we dissect the makefile. You comments are still appreciated. Thanks, Rasit According to David Mentre: > > Hello, > > > From: Mohammad Shorfuzzaman [mailto:szaman@cs.umanitoba.ca] > > > I've downloaded the necessary tar files in the download directory and > > performed instruction as said in the README file. The > > completiion of "make" ends > > with these errors: > > > > makeinfo: Removing output file > > `/root/ixp1200_linux/src/glibc-2.1.3/manual/libc.info' due to > > errors; use > > --force to preserve. > > make[3]: *** [libc.info] Error 2 > > make[3]: Leaving directory > > `/root/ixp1200_linux/src/glibc-2.1.3/manual' > > make[2]: *** [manual/subdir_install] Error 2 > > make[2]: Leaving directory `/root/ixp1200_linux/src/glibc-2.1.3' > > make[1]: *** [install] Error 2 > > make[1]: Leaving directory `/root/ixp1200_linux/build/glibc-2.1.3' > > make: *** [glibc] Error 2 > > Your are not giving us enough information. You should give us the error > messages from the command executed before make aborts the compilation. > > As a rule of thumb, always give the last command executed by make. > > Anyway, I would say that your compilation fails to produce documentation, > probably because you don't have a needed package (info probably). > > Best regards, > d. > -- > David Mentré <mentre(a)tcl.ite.mee.com> - Research engineer > Mitsubishi Electric ITE-TCL / European Telecommunication Research Laboratory > > Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 > http://www.mitsubishi-electric-itce.fr > -- M. Rasit Eskicioglu E-mail: rasit(a)cs.umanitoba.ca Department of Computer Science Phone : (204) 474-8835 (Office) 528 Machray Hall (204) 474-8313 (Messages) University of Manitoba Fax : (204) 474-7609 Winnipeg, Manitoba R3T 2N2 Canada URL : http://www.cs.umanitoba.ca/~rasit

2 2

Receive error from giga port
by Wong Kim Sing 21 Jun '03

21 Jun '03

Hi, I had this problem of receiving error packet from the giga port, here is how the test go. I had created some packets in the microengine, e.g. move($$dxfer0, 0xfffffff1) move($$dxfer1, 0xfffffff3) move($$dxfer2, 0xfffffff5) move($$dxfer3, 0xfffffff7) move($$dxfer4, 0xfffffff9) move($$dxfer5, 0xfffffffb) move($$dxfer6, 0xfffffffd) move($$dxfer7, 0xffffffff) sdram[write, $$dxfer0, packet_buf_addr, 0, 4], ctx_swap move($$dxfer0, 0xfffffff1) move($$dxfer1, 0xfffffff3) move($$dxfer2, 0xfffffff5) move($$dxfer3, 0xfffffff7) move($$dxfer4, 0xfffffff9) move($$dxfer5, 0xfffffffb) move($$dxfer6, 0xfffffffd) move($$dxfer7, 0xffffffff) sdram[write, $$dxfer0, packet_buf_addr, 4, 4], ctx_swap And I send out this packet to the giga port using the "L3fw8_1.uc" microcode from intel reference design. Result obtained as below: 19:21:03.445227 ff:f0:ff:ff:ff:f1 ff:ff:ff:f1:ff:ff ffff 116: fff2 ffff fff5 ffff fff4 ffff fff5 ffff fff6 ffff fff9 ffff fff8 ffff fff9 ffff fffa ffff fffd ffff fffc ffff fffd ffff fffe ffff fff1 ffff fff0 ffff fff1 ffff fff2 ffff fff5 ffff fff4 ffff fff5 ffff fff6 On the first row and the fifth row, it should be "fff3" and "fff5" respectively, but it become "fff2" and "fff4", there is one bit being modified. And also from 2nd row onward,there is some duplication occur, the 2 words "ffff fff5" has been repeated two time in row 4 and row 6. Is there anyone has this similar problem before or do you have any ideal of solving this, please send a email, thank you. Mike Wong Kim Sing R&D Engineer Institute for Communications Research 20 Science Park Road TeleTech Park #02-34/37 Singapore Science Park II Singapore 117674 Tel: 65 68729030 DID : 65 68709320 Fax: 65 67795441 Email: wongks(a)i2r.a-star.edu.sg Website: http://www.i2r.a-star.edu.sg

2 1

IXP1200 timings.
by Liam.Noonan 19 Jun '03

19 Jun '03

Hi, As part of my research into network processors I am examining the IXP1200. I am trying to obtain information regarding the number of cycles/ length of time it takes the IXP1200 to peform the following tasks. 1, move an mpacket from the a port to rfifo 2, moving mpackets from rfifo to the Microengines, SDRAM 3. Moving mpackets from SDRAM and the Microengine to TFIFO 4. Moving mpackets from TFIFO to an out going port. 5. access times for accessing SRAM. I have reviewed the various literature and publications provided by Intel, but obtaining this information is proving challenging. Any information would be appreciated. Thanks Liam Noonan Dept EC&E University Of Limerick Ireland

3 2

Re: [ixp1200] Question on uEngine C compiler
by Shyamal Pandya 13 Jun '03

13 Jun '03

That is because there are a total of 64 sram xfer registers, so each of the four contexts of a microengine gets 16 locally addressable xfer regs, out of which 8 are read and 8 are for write. Maybe you should use global addressing for your xfer registers, which will give you access to more than 8 read xfer registers. Of course will mean you can access fewer local registers. -- Shyamal Pandya Arizona State University Addr: 920 S Terrace Rd #102 Tempe AZ 85281 Phone: 1-480-966-1982 >From: "xtan" <xtan(a)csnet1.cs.tsinghua.edu.cn> >Reply-To: ixp1200(a)CS.Princeton.EDU >To: <ixp1200(a)CS.Princeton.EDU> >Subject: [ixp1200] Question on uEngine C compiler >Date: Fri, 30 May 2003 20:49:31 +0800 > >Hello everybody, >Recently, I encountered a problem that I have to read 16 long words from >SRAM one at a time. But the sram_read intrinsic function can only support >up >to 8 long words. Besides, implementing 16 sram_reg in array format (ex. >X[16]) seems impossible.(Only 8 are allowed) > >Does anyone have good suggestions? Thanks in advance. > >Zhangxi Tan > _________________________________________________________________ Protect your PC - get McAfee.com VirusScan Online http://clinic.mcafee.com/clinic/ibuy/campaign.asp?cid=3963

4 3

Help reg problem with scheduler-worker design.
by Jagannathan Iyer Venkatesan 09 Jun '03

09 Jun '03

Hi, I have succeded in making the scheduler-worker design work for packets that are less than 214 bytes (size includes all the headers including the MAC header size; with UDP, the size of UDP data is 170 bytes). I have avoided reading stale rcv_rdy_lo flag by looping around using the RCV_RDY_CNT register. But when I increase the packet by 215 byte (in UDP datagram, this translates to 171 bytes of UDP data), I see overflow in the MAC registers. Also, the scenario is peculiar and is explained as follows : I use my UDP client which sends 1) a single 22 byte data first (always) [64 byte packet after MAC layers' encapsulation]. No problem with this packet. /* Also, any packet size above this will make it successfully. */ 2) Send packets of data size 171 bytes repeatedly!! The strange this, every other 171 packet makes it across to the destination. The first one does not cause any MAC overflow but the next one does cause a MAC overflow. The third 171 one makes it across the board. The fourth 171 fails. This goes on. (171 + 44 = 215 after MAC encapsulation. 64 *3 = 192; 64*4 = 256; and so the last chunk has ractional data of size 23 bytes) { the same packet sending can be repeated with data size = 172,173, etc. } 3) If I increase to very large packets, eg 234 butes, the first one and subsequent ones never make it across the board. Between packets, I have a getchar() and on key stroke, I send packets. The machines are in a linear configuration, i.e source <==> IXP <==> destn. The destn does not send any packet back. I think there is no overflow of the RCV_REQ_CNT byte in the RCV_RDY_CNT register because just 4 chunks have come. Can anyone suggest why I am getting this problem ? Any pointers will be very helpful. Jagan. PS : To gain more insight, the design looks almost as the transaltion of the following pseudocode. The thread allocation to the port is static and there is only one thread that takes care of receive from one port. The scheduler is working as follows : while(1) { read_reg(rcv_rdy_lo); old = read( RCV_RDY_CNT); /* reads value as X*/ if(rcv_rdy_lo==0) continue; see_which_microengine_has_to be informed(); construct_the_rcv_req(other_uc_TID); // so that the correct // microengine is signalled write_to_rcv_req(); new=read(RCV_RDY_CNT);/*reads value as X if transfer is not over reads value as X+1 if transfer is over. while(old <=new) { new=read(RCV_RDY_CNT); /* if X+1, then quit. */ } The worker thread looks like : while (1) { wait_for_signal(start_receive); read_the register(rcv_cntl); read_the packet_from_fifo(); eop=process_the packet(); if(eop) { peek intocache and tranmit the packet to the outgoing i/f } else { assemble the packet till eop comes. } }

3 2

Question on uEngine C compiler
by xtan 30 May '03

30 May '03

Hello everybody, Recently, I encountered a problem that I have to read 16 long words from SRAM one at a time. But the sram_read intrinsic function can only support up to 8 long words. Besides, implementing 16 sram_reg in array format (ex. X[16]) seems impossible.(Only 8 are allowed) Does anyone have good suggestions? Thanks in advance. Zhangxi Tan

1 0

Ethernet to Giga port packet forwarding
by skdas＠i2r.a-star.edu.sg 29 May '03

29 May '03

Hi, I'm a bignner in this area. My task is to send/receive packet from/to Ethernet to/from Giga port using microcode. Anyone have the source code for this, else any suggestions are welcome. With thanks and regards, Santos I2R, Singapore

3 2

Installing problems
by Alejandro Moreno 27 May '03

27 May '03

We have problems installing the enp-2505 board. We followed IXA Education Workstation Setup Guide step by step. The problem is in section 7 (Booting ENP-2505 board), after execute the manual boot in linux terminal, there is no response... we check pc serial communication and it is good, but the enp-2505 board doesn't have serial communication. It is important to say that our pc has different characteristics of the one mentioned in the guide: - We don't have Dell Precision WS, our pc is generic (Pentium4 on intel motherboard). - WinXP (no problem with vmware in linux, is it important that pc most have Win2000?). - One hard disk (no booting problems). best regards!

2 1

RE: [ixp1200] using addresses of labels
by Arthur Berkovitch 27 May '03

27 May '03

Hi Cyrus, Use the JUMP instruction: jump[register, label#], targets [label1, label2, ...labeln], optional_token Also, you may find the .func_table directive useful for your needs. If wanted, you can export the labels addresses to core applications with the .export_func directive. take care, Arthur -----Original Message----- From: Cyrus Hall [mailto:hallcp@cs.colorado.edu] Sent: Wednesday, May 14, 2003 1:28 AM To: ixp1200 List Subject: [ixp1200] using addresses of labels Hi there all- I'm currently trying to build a table of address to parts of a filter I've written. IE, you have a value, index into the table, and jump to the associated address in code. The jumping is simple enough, save the PC and replace it, give up control, and wait for the ctx switch back in. Not hyper efficient, but not bad when you're only filter one or two fields. Returning is simple enough as well. The problem I'm having is actually get the address of code. This clearly needs to be done at compile time (there doesn't appear to be a linker involved in loading code onto the ME's), and would seem to be as simple as replacing the symbolic label with it's final address. Yet, there seems to be no way to do something like: immed32[var, label#:] Has anyone done anything like this and\or know how? Thanks, Cyrus

3 4