Hi, thanks for all the help so far, but I still have a few questions
(potentially stupid, as always):
How are the microACEs distributed among the microengines when using a
default configuration file? I am unable to find any documentation on
this subject (The ixsys.* files are generally poorly documented :)).
How can I control this distribution? Can I give any directives in the
configuration file to load an ACE on two engines, or is this done
programatically, i.e., when initializing the ace from the core?
How about the number of threads running on the engine? What is the
default and how can I control it?
Does the IngressACE do any processing of packets, or does it only define
the macros that I use in my dispatch loop? According to the design
documents and the source the latter seems to be it, but I'd like to be
100% sure.
Does anyone know how many cycles it takes the egress to transfer a 1024
byte large packet from SDRAM to the link? :) -Or where can I find
information about how the egress really works?
In advance, thanks!
Info: ENP-2505, embedded linux, Intel SDK 2.01
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Øyvind Hvamstad