Hi, I am using the Princeton firmware and Vera software as the base, but WITHOUT the Vera model, in which you can plugin forwarders into the input processing loop. I am basically trying to let the input thread just move packets as fast as it can into the DRAM . (something akin to vera with IP-- hardcoded into the input loop) I am having problems with higher packet rates for large packets. So for 1500 byte packets, I can pump in 1250pps (which is 15Mbps approx) across a pair of ports. But if I try to split this load across two sets of ports, i.e send in 625pps, then I start getting port overflows. To avoid these overflows, I have to reduce the rate to almost like 3Mbps with 1500 byte packets. I am currently using only 1 FIFO slot and 64 bytes on the port buffer. Will using more slots from the FIFO (for eg. I can use 4 slots per port if I am only supporting 4 ports) and maybe 128 bytes on the port reduce the overflows significantly or by a appreciable factor? If there are any INTEL folks on this list, can you point out or advise whether the overflows could just be due to the input contexts not been able to get back to the port fast enough? Will draining out the entire packet at one go and then passing control to the other contexts work better than draining out 1 MP at a time and then immediately passing control to the other thread? Maybe draining out the entire packet would result into overflows on the other ports and would be no better? I have the ACE framework from Intel set up too, so maybe I can try out the same experiment on that and see how it behaves for large packets. I am not sure if I am very clear with my questions, but if somebody wants, I can reclarify. Thanks, - Abhijeet