You have Evaluation Systems based on the A-3 step of the IXP1200 Network Processor. Buried at the bottom of the cover letter included with your systems is the following:
"Also note, the IXP1200 Network Processor on this evaluation system runs at a core frequency of 176 MHz. This temporary condition is due to a lack of component availability used to design the evaluation board."
Intel officially supports 166 MHz and now 200 MHz versions of the IXP1200. Our first version of the Evaluation System run at 176 MHz as indicated above.
Susan Yost IXP1200 Tech Marketing
I don't find the "core frequency of 176" in the printed documentation that came with the systems, though now that you mention it, I seem to remember reading that line somewhere. Could you be more specific about its location? (I'm hoping to find other important information there.) ----------------------------------------------------------------------------- My routine queries the MMU for its "ID_CHIP" function: static inline int mmu_id_chip (void) { register int x ; __asm__ __volatile__ ( "mrc 15, 0, %0, c0, c0, 0" : "=r" (x)) ; return x ; } and returns: mmu_id_chip 6901c120 which translates to [IMP]lementer = 0x69 (the documentated constant) [ARCH]itecture version = 0x01 (the documentated constant) [P]art [N]umber = 0xc12 (the documented constant for IXP1200) [REV]ision number = 0x0 I think our other system (which is currently dead) showed a higher revision number. The working system has a revision number of zero, which I'm of the impression is a earlier rev that A-3? Unlike the dead system, this board had come in a unsealed bag with no plugs for the gigabit ports, so might have been "previously owned". Do we have a revision mismatch from what we are supposed to have? ----------------------------------------------------------------------------- If my fast_clock is running at 176 MHz, what is my slow clock running at? The documentation for the PLL_CFG register on page 28 of the "IXP1200 Network Processor Specification Update (June 2000)" specifies that bits 4:0 being equal to 0x10 means 162.20 MHz if my slow_clock frequency is 3.6864 MHz. The ratio of these two constants is just about correct, given the relative frequency of interrupts generated by timers based on them. If you are telling me that my fast_clock is really running at 176Mhz, then what is my slow clock running at then? Or are you telling me that I should set bits 4:0 of the PLL_CFG register to 0x11 to make it run at 176.95Mhz as the documentation indicates? In either case, is it possible to get the exact values of both the slow_clock and the fast_clock? (down to the unit Hz) Thanks! -- Perry