29 Oct
2003
29 Oct
'03
3:28 p.m.
Hi, I have question: IX bus speed:66Mhz Core clock freq:166Mhz To check the receive ready flag(rcv_rdy_lo) it requires 11cycles. Details: Queue: 4 cycles Dequeue: 1 cycle Finish and sends signal to thread : 2 cycles thread receives the completion signal: 4 cycles cycles based on core clock frequency My question is: Is their a way to find the cycle counts(for each step) without actually running the code? Thanks, Basu ----------------------------------------- This email was sent using DACafeMail. Get Your FREE 25 MB eMail Account Now. http://cafemail.dcccafe.com