I am setting bit 5 in RDYBUS_TEMPLATE_CTL, but the IXP bus still appears to be running in Big Endian mode. Here are the details: B0 board in eval chassis Proprietary OS with the ARM running in Little Endian mode. 1.0 pwd_2f with only changes to the SDRAM packet base address In hw_init.uc just after the ready bus has been programmed immed[$xfer2, 0xF20] csr[write, $xfer2, RDYBUS_TEMPLATE_CTL], CTX_SWAP I have ARM code running which dequeues packets off SRAM/SDRAM as they were placed by the microengine receive threads. Ultimately I want to DMA the packet data across the PCI bus. However, because the IX bus is running in Big Endian mode, the packets appear in SDRAM byte swapped on longword boundaries (see HRM, pg 6-55). I know if I do a longword copy of the packet, the copied packet will appear in the correct order. But I want to avoid this overhead. In fact, this is probably the reason the PETH driver works? My thinking is, if I can get the IX bus running in Little Endian mode, the packet data will be in the correct order for my DMA over the PCI bus. Agree? Has anyone run pwd_2f with LITTLE_ENDIAN defined and Little Endian (bit 5) set in the RDYBUS_TEMPLATE_CTL? If you have: Where did you set the RDYBUS_TEMPLATE_CTL? What OS are you running and do you have the ARM running in Little or Big Endian (although this should not matter??) Are you seeing the packet data in Little Endian format? Robert Joe (858) 391 1849