I doubt you're still facing this problem, but I just had to figure it out myself, so just in case, here is the code: #macro read_cycle_cnt[new_cnt_0, new_cnt_1] xbuf_alloc($clk, 2) csr[read, $clk[0], cycle_cnt], ctx_swap alu[new_cnt_0, --, B, $clk[0]] alu[new_cnt_1, --, B, $clk[1]] xbuf_free($clk) #endm By default, cycle_cnt runs at 166 MHz. That would overflow a single 32-bit register in a few seconds, so the value is held in two registers instead. The first 32 bit reg ($clk[0]) contains the number of times the second reg ($clk[1]) has overflowed. $clk[1] contains the clock cycle count. The values are stored unsigned. Cyrus On Fri, 2003-05-23 at 08:18, Liam.Noonan wrote:

Hi,

As part of my research into network processors I am examining the IXP1200.

I am trying to obtain information regarding the number of cycles/ length of time it takes the IXP1200 to peform the following tasks.

1, move an mpacket from the a port to rfifo 2, moving mpackets from rfifo to the Microengines, SDRAM 3. Moving mpackets from SDRAM and the Microengine to TFIFO 4. Moving mpackets from TFIFO to an out going port. 5. access times for accessing SRAM.

I have reviewed the various literature and publications provided by Intel, but obtaining this information is proving challenging.

Any information would be appreciated.

Thanks Liam Noonan Dept EC&E University Of Limerick Ireland