Colin, Beware bit 16.8 in the PHY register set. 10MB half-duplex gives (by default) a loopback at the PHY. Best to avoid this configuration, or talk to the PHY and change this bit setting. Rgds Mick -----Original Message----- From: Colin Flanagan [mailto:colin.flanagan@ul.ie] Sent: 23 July 2003 09:40 To: ixp1200@CS.Princeton.EDU Subject: [ixp1200] excessive collisions on 10 Mbit/s ethernet with BridalVeil Card Hello, I am working with the IXP1200 book by Johnson & Kunze, and am trying to get the "single thread receive" code from chapter 5 to work successfully on the BridalVeil board. To this end I have written my own drivers for the octal MAC and have modified ue.o to reflect the 64-bit bi-directional IX bus. I can get everything to work and have the IXP1200 receiving packets successfully from a Smartbits over a 10Mbit/s simplex Ethernet link. However, I get excessive collisions on the link, these can range from 0.14 collisions per packet sent to 1.2 collisions per packet sent. This seems like very unusual behaviour. I wonder if anyone else has seen anything like this? Interestingly, the rate of collisions on the link seems to be related quite sensitively to the program running on the ready bus sequencer. With 12 RxRdy MAC0 instructions running on the RBS, there are no collisions at all. With a single RxRdy MAC0 followed by 11 NOP1 instructions, the rate of collisions per packet sent is 0.14. With alternating RxRdy MAC0 / TxRdy MAC0 pairs (repeated 6 times), I get 1.2 collisions per packet transmitted from the Smartbits. With 11 RxRdy MAC0 instructions and a single TxRdy MAC0 instruction, the rate is 0.7 collisions per packet transmitted from the Smartbits. In all cases the RDYBUS_SYNCH_COUNT_DEFAULT register is set to 0. The IX bus is running at 66MHz. I find this quite confusing, surely there should be no need for any collisions on a link with only one source (the Smartbits)? One thought that has occurred to me, is the IXF440 applying backpressure to the link? I can't see how this would happen though, in my understanding only a Flwctl instruction can cause backpressure to be applied. Alternatively, is the repetition rate of the ready bus program significant? All the RBS programs I have tried take 36 cycles, at 66MHz this should allow an adequate rate of sampling of the status bits. If anyone else has encountered problems like this, or can give me pointers to where I might be going wrong, I'd be very grateful to receive them. Thanks, Colin Flanagan Dept of Electronic & Computer Engineering University of Limerick Ireland PS FBI setup I am using: RCV_RDY_CTL = 0 XMIT_RDY_CTL = 0 FLOWCTL_MASK = 0 RDYBUS_SYNCH_COUNT_DEFAULT = 0 RDYBUS_TEMPLATE_CTL = 0xf00