August 2014 - talks - lists.cs.princeton.edu

2-3pm Fri Aug 29 talk on scaling social search
by Jennifer Rexford 29 Aug '14

29 Aug '14

Speaker: Siddhartha Bannerjee Title: Scaling Social Search - PageRank Estimation for Large Networks When and Where: 29th August (Friday) at 2:00 PM in Room 402 in the CS bldg. Abstract: Although effective search is one of the great successes of the internet, social search lags far behind. A major hurdle is the complexity of existing algorithms for estimating Personalized PageRank -- a generalization of PageRank which measures centrality with respect to a fixed node in a network. In particular, to estimate PageRank values up to the required accuracies, existing algorithms need time which scales linearly in the network size -- this renders them infeasible for real-time social search. In this talk, I will present FAST-PPR, the first algorithm for Personalized PageRank estimation with an average running-time guarantee which is sublinear in the network size. This speedup is achieved via a combination of linear algebraic techniques and random walks; this new approach may prove useful in other estimation problems on networks. Moreover, I'll present detailed empirical studies on numerous large networks, wherein FAST-PPR dramatically outperforms existing algorithms -- for example, with target nodes sampled according to popularity, on the 2010 Twitter graph with 1.5 billion edges, FAST-PPR has a 160 factor speedup compared to the state-of-the-art. Joint work with Peter Lofgren, Ashish Goel and C. Seshadri. Paper available at http://arxiv.org/abs/1404.3181.

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talk on Tilera processor architecture, Sept 11 4:30 pm, E-Quad B205 - Matthew Mattina
by Jennifer Rexford 18 Aug '14

18 Aug '14

> > > Speaker: Matthew Mattina > Tilera > Title: Architecture and Performance of the TILE-Gx72 ManyCore Processor > Date: Thursday, September 11, 2014 > Time: 4:30 p.m. > Room: E-Quad, Room B205 > Host: Prof. David Wentzlaff > > Abstract: This talk describes the Tilera TILE-Gx processor architecture, discusses the design choices that result in high throughput performance and power-efficiency, and presents performance results on representative applications for the 72-core TILE-Gx72, the flagship processor in Tilera's TILE-Gx family. This processor family is comprised of a series of high-performance, low-power 64-bit manycore processor SoCs, tightly coupled with high performance packet processing. These highly integrated processors deliver industry-leading performance and performance-per-watt in the embedded networking, cyber security, and high throughput computing markets. Of particular interest is the iMesh network-on-chip, which scales to 100s of cores and provides high-speed interconnection of all on-die elements and cache coherence across the chip. > > Biography: Mr. Mattina is the Chief Technology Officer at Tilera and is responsible for overall processor strategy and technology. As processor architect at Tilera, he co-led the design of the 64-core TILE-Pro, and the 9- to 72-core TILE-Gx processor families. Prior to Tilera, Mr. Mattina was with Intel Corporation where he was co-lead architect for the Tukwila Multicore Processor, supervising a team of architects and designers. At Intel, Mr. Mattina invented and designed the Intel Ring Uncore Architecture, used across Intel's x86 multicore processor designs. This technology won the Intel Achievement Award in 2010. Prior to Intel, he was an architect and circuit design engineer at Digital Equipment Corporation, working on the Alpha EV7 and EV8 processors. Mr. Mattina also served as Technical Leader at Cisco Systems in the TelePresence Infrastructure Business Unit, where he contributed to the hardware and software design of next-generation high-definition video conferencing products. He has been granted over 20 patents and has published journal and conference papers relating to CPU design, multicore processors, and cache coherence protocols. Mr. Mattina holds a BS in Computer and Systems Engineering from Rensselaer Polytechnic Institute and a MS in Electrical Engineering from Princeton University.

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FPO: August 12, 2014, at 10am in CS 402 (Yuri Pritykin)
by Nicki Gotsis 05 Aug '14

05 Aug '14

Yuri Pritykin will present his FPO on Tuesday, August 12, 2014 at 10am in CS 402. The members of his committee are Mona Singh, advisor; Bernard Chazelle and Olga Troyanskaya, readers; Andrea LaPaugh and Vivek Pai, non-readers. A copy of his/her thesis, is available in Room 310. Everyone is invited to attend his/her talk. Nicki Gotsis Graduate Coordinator Room 310, Computer Science (609) 258-5387 ngotsis(a)cs.princeton.edu

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