October 2018 - talks - lists.cs.princeton.edu

EE Seminar - Thursday, October 18, 2018, 4:30pm, E-Quad B205, Ayfer Ozgur Aydin, Stanford
by Emily Lawrence 11 Oct '18

11 Oct '18

Department of Electrical Engineering Seminar Series Speaker: Prof. Ayfer Ozgur Aydin Stanford University Title: A Geometric Approach to two Problems in Networks: Learning High-Dimensional Distributions and Communication with Relays Date: Thursday, October 18, 2018 Time: 4:30 pm Room: Engineering Quadrangle B205 Host: Prof. Yuxin Chen Abstract: We investigate the pivotal role geometry can play in characterizing the fundamental limits of information flow in two different network problems. We first consider a classical problem in network information theory: characterizing the capacity of a so-called relay channel. Even though the relay channel has been one of the central problems in network information theory, its capacity remains unknown for almost four decades. We solve an open problem posed by Cover in 1987. This problem, which Cover calls the "Capacity of the Relay Channel", corresponds to characterizing the capacity of this channel at one special operating point. Our approach is geometric and builds on an extension we develop for the isoperimetric inequality on a high-dimensional sphere. We then turn to another network problem, where the end goal is not to communicate a message but learn a high-dimensional distribution or parameter from its distributed samples under communication constraints. We first provide a geometric characterization of Fisher information from quantized samples. We then use this characterization to prove tight minimax bounds for distributed estimation of common statistical models (such as the product Bernoulli model, multinomial model, dense/sparse Gaussian location models). Our results show that the impact of the communication constraint can be drastically different depending on the tail behavior of the score function of the model. Some of our results recover or strengthen existing results in this area with simpler and more transparent proofs. We conclude with a discussion on future directions in the intersection of geometry and information theory. First part of the talk is joint work with Xiugang Wu and Leighton Barnes. Second part is joint work with Leighton Barnes, Yanjun Han and Tsachy Weissman. Bio: Ayfer Ozgur received her Ph.D. degree in 2009 from the Information Processing Group at EPFL, Switzerland. In 2010 and 2011, she was a post-doctoral scholar at the same institution. She is an Assistant Professor in the Electrical Engineering Department at Stanford University since 2012. Her research interests include distributed communication and learning, wireless systems, and information theory. Dr. Ozgur received the EPFL Best Ph.D. Thesis Award in 2010, an NSF CAREER award in 2013, the Okawa Foundation Research Grant and the IEEE 2018 Communication Theory Technical Committee (CTTC) Early Achievement Award in 2018. This seminar is supported with funds from the Korhammer Lecture Series.

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REMINDER: Speaker-Sreepathi Pai, tomorrow at 12:30
by Emily C. Lawrence 11 Oct '18

11 Oct '18

Speaker Sreepathi Pai from University of Rochester Friday, October 12, 2018 - 12:30pm Computer Science - Room 105 Host: Tyler Sorensen and Margaret Martonosi “High-performance Graph Processing on GPUs” Abstract: Back in 2013, implementing high-performance graph algorithms for GPUs required manual coding in CUDA, a slow and difficult process. To significantly lower the level of effort required, we created IrGL , a language and compiler specifically for generating high-performance graph algorithm implementations for GPUs. Powered by three throughput optimizations, the IrGL -generated code outperformed nearly all handwritten graph algorithms achieving speedups of up to 6x. Freed from the drudgery of writing low-level code, IrGL has allowed us to look at a number of problems revolving around graphs. We've used the high-performance implementations to identify key memory system bottlenecks that limit performance on current GPU architectures. We've also translated graph database queries to IrGL and executed them on GPUs. In the course of extending this to the general problem of subgraph isomorphism (a key primitive in graph databases), we were named GraphChallenge 2017 champions for our implementation of the triangle-counting and k-truss problems. Along the way, we also built Groute , a runtime for asynchronous multi-GPU graph analytics that has achieved order-of-magnitude improvements over existing synchronous implementations. We sped up exhaustive testing of software by traversing graphs that were too big to materialize in memory. Recently, we have also used IrGL's ability to generate hundreds of variants of the same graph algorithm to explore correctness and performance portability issues on GPUs. Many interesting questions still remain unexplored, however, and I will summarize our current efforts in this area. [Joint work with Keshav Pingali , Tal Ben-Nun, Michael Sutton, M. Amber Hassaan , Chad Voegele , Yi-Shan Lu, Ahmet Celik , Milos Gligoric , Sarfraz Khurshid , Tyler Sorensen and Alastair Donaldson] Bio: Sreepathi Pai is an Assistant Professor of Computer Science at the University of Rochester. His research interests are in compilers, programming languages and implementation, performance models and computer architecture. His most recent research has revolved around the IrGL compiler that produces high-performance GPU code for graph algorithms. He earned his PhD at the Indian Institute of Science and his B.E. in Computer Engineering at the University of Mumbai. Prior to joining the Department of Computer Science at Rochester, he was a Postdoctoral Fellow at the University of Texas at Austin.

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Colloquium Speaker-Andy Myers '96, TODAY at 12:30
by Emily C. Lawrence 09 Oct '18

09 Oct '18

Colloquium Speaker Andy Myers ’96 from Jane Street Tuesday, October 9, 2018 - 12:30pm Computer Science - Room 105 Host: Jennifer Rexford & David Walker *Lunch available for talk attendees at 12:00 pm * “Trading Networks” Abstract: The talk will discuss some of the unique ways in which trading firms use (and misuse) various bits of technology (switches, layer-1 devices, microwaves, FPGAs), to build networking infrastructure that achieves their goals. Bio: Andy Myers has been building low latency trading systems at Jane Street since 2014. Previously he was a Systems Architect at GETCO. He received his A.B. from Princeton in 1996 and his MS from Carnegie Mellon in 1998.

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Speaker-Sreepathi Pai, Friday, October 12
by Emily C. Lawrence 08 Oct '18

08 Oct '18

Speaker Sreepathi Pai from University of Rochester Friday, October 12, 2018 - 12:30pm Computer Science - Room 105 Host: Margaret Martonosi “High-performance Graph Processing on GPUs” Abstract: Back in 2013, implementing high-performance graph algorithms for GPUs required manual coding in CUDA, a slow and difficult process. To significantly lower the level of effort required, we created IrGL , a language and compiler specifically for generating high-performance graph algorithm implementations for GPUs. Powered by three throughput optimizations, the IrGL -generated code outperformed nearly all handwritten graph algorithms achieving speedups of up to 6x. Freed from the drudgery of writing low-level code, IrGL has allowed us to look at a number of problems revolving around graphs. We've used the high-performance implementations to identify key memory system bottlenecks that limit performance on current GPU architectures. We've also translated graph database queries to IrGL and executed them on GPUs. In the course of extending this to the general problem of subgraph isomorphism (a key primitive in graph databases), we were named GraphChallenge 2017 champions for our implementation of the triangle-counting and k-truss problems. Along the way, we also built Groute , a runtime for asynchronous multi-GPU graph analytics that has achieved order-of-magnitude improvements over existing synchronous implementations. We sped up exhaustive testing of software by traversing graphs that were too big to materialize in memory. Recently, we have also used IrGL's ability to generate hundreds of variants of the same graph algorithm to explore correctness and performance portability issues on GPUs. Many interesting questions still remain unexplored, however, and I will summarize our current efforts in this area. [Joint work with Keshav Pingali , Tal Ben-Nun, Michael Sutton, M. Amber Hassaan , Chad Voegele , Yi-Shan Lu, Ahmet Celik , Milos Gligoric , Sarfraz Khurshid , Tyler Sorensen and Alastair Donaldson] Bio: Sreepathi Pai is an Assistant Professor of Computer Science at the University of Rochester. His research interests are in compilers, programming languages and implementation, performance models and computer architecture. His most recent research has revolved around the IrGL compiler that produces high-performance GPU code for graph algorithms. He earned his PhD at the Indian Institute of Science and his B.E. in Computer Engineering at the University of Mumbai. Prior to joining the Department of Computer Science at Rochester, he was a Postdoctoral Fellow at the University of Texas at Austin.

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Reminder: Colloquium Speaker-Andy Myers '96, tomorrow at 12:30
by Emily C. Lawrence 08 Oct '18

08 Oct '18

Colloquium Speaker Andy Myers ’96 from Jane Street Tuesday, October 9, 2018 - 12:30pm Computer Science - Room 105 Host: Jennifer Rexford & David Walker *Lunch available for talk attendees at 12:00pm* “Trading Networks” Abstract: The talk will discuss some of the unique ways in which trading firms use (and misuse) various bits of technology (switches, layer-1 devices, microwaves, FPGAs), to build networking infrastructure that achieves their goals. Bio: Andy Myers has been building low latency trading systems at Jane Street since 2014. Previously he was a Systems Architect at GETCO. He received his A.B. from Princeton in 1996 and his MS from Carnegie Mellon in 1998.

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Colloquium Speaker-Andy Myers '96, Tuesday, October 9
by Emily Lawrence 02 Oct '18

02 Oct '18

Colloquium Speaker Andy Myers '96 from Jane Street Tuesday, October 9, 2018 - 12:30pm Computer Science - Room 105 Host: Jennifer Rexford & David Walker "Trading Networks" Abstract: The talk will discuss some of the unique ways in which trading firms use (and misuse) various bits of technology (switches, layer-1 devices, microwaves, FPGAs), to build networking infrastructure that achieves their goals. Bio: Andy Myers has been building low latency trading systems at Jane Street since 2014. Previously he was a Systems Architect at GETCO. He received his A.B. from Princeton in 1996 and his MS from Carnegie Mellon in 1998.

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TODAY 10/1 at 4:30pm in B205 - Chandra Nair, Chinese University of Hong Kong
by Emily Lawrence 01 Oct '18

01 Oct '18

EE SEMINAR SERIES Speaker: Chandra Nair, Chinese University of Hong Kong Title: Non-Convex Optimization And Multiuser Information Theory Day: Monday, October 1, 2018 Time: 4:30 pm Room: B205 Engineering Quadrangle Host: Prof. Peter Ramadge Abstract: Capacity regions in multiuser information theory were traditionally established using an achievability argument and converses to corresponding rate regions. Recently, however, capacity regions have been established, for non-trivial and important classes of channels (such as additive Gaussian noise models and others), by optimizing functionals on probability spaces generated from inner or outer bounds and showing that the bounds match for these channels. Optimization ideas have also been used to determine if certain achievable regions proposed in the literature are optimal or sub-optimal in general. The study of these non-convex optimization problems required developing new insights and techniques. In this talk, I will outline the ideas involved in obtaining the results, as well as illustrate the relationship of these problems to hypercontractivity and related notions studied primarily outside information theory. I will present some unifying observations across the family of optimization problems that we have managed to solve, and state some elementary instances of similar problems whose solutions would be of immense interest. Bio: Chandra Nair is an Associate Professor with the Information Engineering department at The Chinese University of Hong Kong. His research interests and contributions have been in developing ideas, tools, and techniques to tackle families of combinatorial and non-convex optimization problems arising primarily in the information sciences. His recent research focus has been on studying the optimality of certain inner and outer bounds to capacity regions for fundamental problems in multiuser information theory. He, along with his doctoral student Yanlin Geng, received the 2016 Information Theory Society paper award for developing a novel way to establish the optimality of Gaussian distributions. A proof of the Parisi and Coppersmith-Sorkin conjectures in the Random Assignment Problem constituted his doctoral dissertation; and he resolved some conjectures related to Random Energy model approximation of the Number Partition Problem during his post-doctoral years. Chandra Nair got his Bachelor's degree, B.Tech(EE), from IIT Madras (India) where he was the Philips (India) and Siemens (India) award winner for the best academic performance. Subsequently he was a Stanford graduate fellow (00-04) and a Microsoft graduate fellow (04-05) during his graduate studies at the EE department of Stanford university. Later, he became a post-doctoral researcher (05-07) with the theory group at Microsoft Research, Redmond. He has been a faculty member of the information engineering department at The Chinese university of Hong Kong since Fall 2007. He was an associate editor for the IEEE Transactions on Information Theory (2014-2016) and is currently a distinguished lecturer of the IEEE Information theory society. He is a fellow of the IEEE. He serves as the Programme Director of the undergraduate program on Mathematics and Information Engineering and the Director of the Institute of Theoretical Computer Science and Communications.

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Save the date for Princeton Research Day - May 9, 2019
by Emily Lawrence 01 Oct '18

01 Oct '18

Save the Date for Princeton Research Day! Posters . Talks . Performances . Art Exhibitions . Digital Presentations Thursday, May 9, 2019 Frist Campus Center <http://researchday.princeton.edu/> researchday.princeton.edu #PRD19 We encourage all academic departments and centers at Princeton to reserve May 9, 2019, for Princeton Research Day, and to support participation by your undergraduates, graduate students, postdoctoral researchers and fellows, and other early career researchers. Princeton Research Day is a celebration of the research and creative endeavors by our undergraduates, graduate students, postdoctoral researchers and fellows, and other early career researchers. The fourth-annual campus-wide event will feature poster presentations, exhibits, performances, selected talks and an award ceremony for outstanding contributions. The all-day event is free and open to the public. Application will open Dec. 3, 2018. Dates to remember: Dec. 3: Call for applications to present at PRD19 Feb. 18: Priority application deadline April 1: Presenters informed of presentation format and given access to edit presentation summaries April 22: Presenter RSVP deadline; last day to edit presentation summaries April 26: PRD19 program becomes available to public May 9: Princeton Research Day More details are available at researchday.princeton.edu <http://researchday.princeton.edu/> . Questions? Contact researchday@princeton <https://owa.princeton.edu/owa/redir.aspx?C=RLzvZJLd5qsfA35tEu-RZUskcIzw1Or- xtqM97sHprDuM74sownUCA..&URL=mailto%3aresearchday%40princeton.edu> .edu <https://owa.princeton.edu/owa/redir.aspx?C=YX0gtaHjrc-9tcOtKgiNyz3ODOIM6cxn odqEzb_K5mX_Wr4sownUCA..&URL=mailto%3aresearchday%40princeton.edu> . Princeton Research Day is a collaborative initiative between the offices of the Dean of the College, the Dean of the Faculty, the Dean of the Graduate School and the Dean for Research, with support from the Office of the Provost. Alice Seneres, Ph.D. Assistant Dean for Academic Affairs Office of the Dean of the Faculty Princeton University 306A Nassau Hall (609) 258-4793 aseneres(a)princeton.edu <mailto:aseneres@princeton.edu>

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