November 2019 - talks - lists.cs.princeton.edu

Speaker Ravi Chugh, Friday Nov 8 at 11am
by Emily Lawrence 06 Nov '19

06 Nov '19

Title: Bidirectional Programming with Direct Manipulation Speaker: Ravi Chugh, University of Chicago Date/Time: Friday, November 8th, 11 AM — 12 PM Location: CS 402 Abstract: Traditional text-based programming environments present users with mental hurdles and tedious, inefficient development workflows. In this talk, I'll describe techniques that aim to improve the user interfaces for programming. What new capabilities can programming languages offer to users, and what new interaction mechanisms can be used to expose the new capabilities? We are developing a prototype programming environment, called Sketch-n-Sketch, to explore these questions. Regarding capabilities, we present program synthesis and repair techniques for "bidirectionally" developing and evaluating programs. Regarding interaction mechanisms, we present "direct manipulation" interfaces for interacting with programs and their execution. These systems augment traditional text-based programming with new program development workflows, which we plan to further improve and evaluate in the future. Bio: Ravi Chugh has been Assistant Professor of Computer Science at the University of Chicago since 2014. His research and teaching interests revolve around programming language technology --- type systems, synthesis algorithms, and other program analysis techniques --- particularly as they relate to challenges in software engineering and human-computer interaction. Ravi received an NSF CAREER Award in 2017, and a Neubauer Fellowship from the University of Chicago in 2015 for innovative and effective undergraduate teaching. Ravi obtained his Ph.D. from the University of California, San Diego in 2013. Picture: http://people.cs.uchicago.edu/~rchugh/static/images/ravi-2018-10.jpg

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Colloquium Speaker: Jeff Mogul, Wednesday 11/13 at 12:30pm
by Emily C. Lawrence 06 Nov '19

06 Nov '19

Distinguished CS Colloquium Speaker Jeff Mogul, Google Networking Infrastructure Wednesday, November 13 - 12:30pm Computer Science - Room 105 Host: Kyle Jamieson [ https://www.cs.princeton.edu/events/25892 | https://www.cs.princeton.edu/events/25892 ] Self-Driving Networks: Is it a good idea to mix AI and computer networks? Just as you wouldn't want to be in a car without seat belts, even if it's a self-driving car, you probably don't want your Self-Driving Network ( SelfDN ) to rely completely on control-theory or ML, no matter how sophisticated or formally verified. While autonomous systems promise to solve many problems that afflict networks, just as they promise to solve many problems that afflict our roadways, they are not immune from a multitude of practical problems and unexpected consequences. At Google, we have been moving towards highly-automated networking, and along the way we have learned a lot about the risks involved, and how to build robust networks in spite of the wonders of automation. I will talk about some of the problems that are likely to afflict SelfDNs as they enter the real world. Bio: Jeff Mogul works on fast, cheap, reliable, and flexible networking infrastructure for Google. Until 2013, he was a Fellow at HP Labs, doing research primarily on computer networks and operating systems issues for enterprise and cloud computer systems; previously, he worked at the DEC/Compaq Western Research Lab. He received his PhD from Stanford in 1986, an MS from Stanford in 1980, and an SB from MIT in 1979. He is an ACM Fellow. Jeff is the author or co-author of several Internet Standards; he contributed extensively to the HTTP/1.1 specification. He was an associate editor of Internetworking: Research and Experience, and has been the chair or co-chair of a variety of conferences and workshops, including SIGCOMM, OSDI, NSDI, USENIX, HotOS , and ANCS.

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Reminder: Tushar Krishna, tomorrow at 12:30
by Emily C. Lawrence 06 Nov '19

06 Nov '19

CS Colloquium Speaker Tushar Krishna from Georgia Tech Thursday, November 7 - 12:30pm E-Quad, B205 Host: Margaret Martonosi [ https://www.cs.princeton.edu/events/25888 | https://www.cs.princeton.edu/events/25888 ] Enabling Continuous Learning through Synaptic Plasticity in Hardware Ever since modern computers were invented, the dream of creating artificial intelligence (AI) has captivated humanity. We are fortunate to live in an era when, thanks to deep learning (DL), computer programs have paralleled, and in many cases even surpassed human level accuracy in tasks like visual perception and speech synthesis. However, we are still far away from realizing general-purpose AI. The problem lies in the fact that the development of supervised learning based DL solutions today is mostly open loop. A typical DL model is created by hand-tuning the deep neural network (DNN) topology by a team of experts over multiple iterations, followed by training over petabytes of labeled data. Once trained, the DNN provides high accuracy for the task at hand; if the task changes, however, the DNN model needs to be re-designed and re-trained before it can be deployed. A general-purpose AI system, in contrast, needs to have the ability to constantly interact with the environment and learn by adding and removing connections within the DNN autonomously, just like our brain does. This is known as synaptic plasticity. In this talk we will present our research efforts towards enabling general-purpose AI leveraging plasticity in both the algorithm and hardware. First, we will present GeneSys (MICRO 2018), a HW-SW prototype of a closed loop learning system for continuously evolving the structure and weights of a DNN for the task at hand using genetic algorithms, providing 100-10000x higher performance and energy-efficiency over state-of-the-art embedded and desktop CPU and GPU systems. Next, we will present a DNN accelerator substrate called MAERI (ASPLOS 2018), built using light-weight, non-blocking, reconfigurable interconnects, that supports efficient mapping of regular and irregular DNNs with arbitrary dataflows , providing ~100% utilization of all compute units, resulting in 3X speedup and energy-efficiency over our prior work Eyeriss (ISSCC 2016). Finally, time permitting, we will describe our research in enabling rapid design-space exploration and prototyping of hardware accelerators using our dataflow DSL + cost-model called MAESTRO (MICRO 2019). Bio: Tushar Krishna is an Assistant Professor in the School of Electrical and Computer Engineering at Georgia Tech. He also holds the ON Semiconductor Junior Professorship. He has a Ph.D. in Electrical Engineering and Computer Science from MIT (2014), a M.S.E in Electrical Engineering from Princeton University (2009), and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi (2007). Before joining Georgia Tech in 2015, Dr. Krishna spent a year as a post-doctoral researcher at Intel, Massachusetts. Dr. Krishna’s research spans computer architecture, interconnection networks, networks-on-chip ( NoC ) and deep learning accelerators - with a focus on optimizing data movement in modern computing systems. Three of his papers have been selected for IEEE Micro’s Top Picks from Computer Architecture, one more received an honorable mention, and two have won best paper awards. He received the National Science Foundation (NSF) CRII award in 2018, and both a Google Faculty Award and a Facebook Faculty Award in 2019. He also received the “Class of 1940 Course Survey Teaching Effectiveness” Award from Georgia Tech in 2018.

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