January 2020 - talks - lists.cs.princeton.edu

Alejandro Newell will present his General Exam "Beyond Objects: Image Understanding as Pixels to Graphs" on Friday, January 17, 2020 at 12pm in CS 401
by Nicki Mahler 10 Jan '20

10 Jan '20

Alejandro Newell will present his General Exam "Beyond Objects: Image Understanding as Pixels to Graphs" on Friday, January 17, 2020 at 12pm in CS 401. The members of his committee are as follows: Jia Deng (adviser), Olga Russakovsky, and Szymon Rusinkiewicz. Everyone is invited to attend his talk, and those faculty wishing to remain for the oral exam following are welcome to do so. His abstract and reading list follow below. Abstract: Tremendous progress has been made teaching computer … [View More]vision systems to recognize objects in images. Each year, these systems can more reliably classify objects and better pinpoint their location in a scene. But a collection of objects is not enough. For full scene understanding, we must understand the connections and relationships between objects. Graphs are an effective way of representing these connections, but are difficult to express given standard approaches for training deep convolutional networks. In this presentation, I will discuss how to supervise a network to predict graphs. I will go over the details of our approach including its application to relationship detection and advantages over existing methods. Reading List: Szeliski, Richard. Computer vision: algorithms and applications. Springer Science & Business Media, 2010. Krizhevsky, Alex, Ilya Sutskever, and Geoffrey E. Hinton. "Imagenet classification with deep convolutional neural networks." Advances in neural information processing systems. 2012. Toshev, Alexander, and Christian Szegedy. "Deeppose: Human pose estimation via deep neural networks." Proceedings of the IEEE conference on computer vision and pattern recognition. 2014. Tompson, Jonathan J., et al. "Joint training of a convolutional network and a graphical model for human pose estimation." Advances in neural information processing systems. 2014. Johnson, Justin, et al. "Image retrieval using scene graphs." Proceedings of the IEEE conference on computer vision and pattern recognition. 2015. He, Kaiming, et al. "Deep residual learning for image recognition." Proceedings of the IEEE conference on computer vision and pattern recognition. 2016. Cao, Zhe, et al. "Realtime multi-person 2d pose estimation using part affinity fields." Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition. 2017. He, Kaiming, et al. "Mask r-cnn." Proceedings of the IEEE international conference on computer vision. 2017. Krishna, Ranjay, et al. "Visual genome: Connecting language and vision using crowdsourced dense image annotations." International Journal of Computer Vision 123.1 (2017): 32-73. Lu, Cewu, et al. "Visual relationship detection with language priors." European Conference on Computer Vision. Springer, Cham, 2016. Xu, Danfei, et al. "Scene graph generation by iterative message passing." Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition. 2017. Oord, Aaron van den, Yazhe Li, and Oriol Vinyals. "Representation learning with contrastive predictive coding." arXiv preprint arXiv:1807.03748 (2018). [View Less]

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Ziyang Xu will present his General Exam "Revisiting Type-Awareness for Automatic Parallelization" on Friday, January 17, 2020 at 10:30am in CS 302
by Nicki Mahler 10 Jan '20

10 Jan '20

Ziyang Xu will present his General Exam "Revisiting Type-Awareness for Automatic Parallelization" on Friday, January 17, 2020 at 10:30am in CS 302. The members of his committee are as follows: David August (adviser), Amit Levy, and Zachary Kincaid. Everyone is invited to attend his talk, and those faculty wishing to remain for the oral exam following are welcome to do so. His abstract and reading list follow below. Abstract: Over the last decade, advances in memory analyses, speculative … [View More]techniques, and parallelization paradigms have dramatically improved the power of automatic parallelization. To be applicable for general-purpose C and C++ codes, parallelizing compilers incorporating these advances work without making use of type information. This study explores the value of making RAPPORT, a state-of-the-art parallelization framework, aware of modern type features when parallelizing Rust programs. We extend RAPPORT with a Rust frontend that brings type information to the IR. New type-aware memory analysis (TAMA) modules bring this information into the RAPPORT's collaborative analysis framework (CAF), allowing these modules to use type information in collaborating with other memory analysis modules to maximize their effect. We measure the extent to which this framework can use Rust type information to uncover more or better automatic parallelization opportunities. Reading List: Books: [1]J. L. Hennessy and D. A. Patterson, Computer architecture: a quantitative approach. Elsevier, 2011. [2]A. W. Appel, Modern Compiler Implementation in ML. New York, NY, USA: Cambridge University Press, 2004. Papers: [1]B. K. Rosen, M. N. Wegman, and F. K. Zadeck, “Global value numbers and redundant computations,” in Proceedings of the 15th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 1988, pp. 12–27. [2]D. G. Clarke, J. M. Potter, and J. Noble, “Ownership Types for Flexible Alias Protection,” in Proceedings of the 13th ACM SIGPLAN Conference on Object-oriented Programming, Systems, Languages, and Applications, New York, NY, USA, 1998, pp. 48–64. [3]A. Diwan, K. S. McKinley, and J. E. B. Moss, “Type-based Alias Analysis,” in Proceedings of the ACM SIGPLAN 1998 Conference on Programming Language Design and Implementation, New York, NY, USA, 1998, pp. 106–117. [4]K. Crary, D. Walker, and G. Morrisett, “Typed memory management in a calculus of capabilities,” in Proceedings of the 26th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL ’99, San Antonio, Texas, United States, 1999, pp. 262–275. [5]G. Ottoni, R. Rangan, A. Stoler, and D. I. August, “Automatic thread extraction with decoupled software pipelining,” in 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’05), 2005, pp. 12 pp. – 118. [6]M. J. Bridges, N. Vachharajani, Y. Zhang, T. Jablin, and D. I. August, “Revisiting the Sequential Programming Model for Multi-Core,” in Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 69-84. IEEE Computer Society, 2007. [7]S. Campanoni, T. Jones, G. Holloway, V. J. Reddi, G.-Y. Wei, and D. Brooks, “HELIX: automatic parallelization of irregular programs for chip multiprocessing,” in Proceedings of the Tenth International Symposium on Code Generation and Optimization - CGO ’12, San Jose, California, 2012, p. 84. [8]N. P. Johnson, H. Kim, P. Prabhu, A. Zaks, and D. I. August, “Speculative Separation for Privatization and Reductions,” in Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation, New York, NY, USA, 2012, pp. 359–370. [9]N. P. Johnson, J. Fix, S. R. Beard, T. Oh, T. B. Jablin, and D. I. August, “A collaborative dependence analysis framework,” in 2017 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), Austin, TX, USA, 2017, pp. 148–159. [10]V. Astrauskas, P. Müller, F. Poli, and A. J. Summers, “Leveraging Rust Types for Modular Specification and Verification,” Proc. ACM Program. Lang., vol. 3, no. OOPSLA, pp. 147:1–147:30, Oct. 2019. [11]S. Apostolakis, Z. Xu, G. Chan, S. Campanoni, and D. I. August, “Perspective: A Sensible Approach to Speculative Automatic Parallelization,” in Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, 2020. [View Less]

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Aninda Manocha will present his General Exam, "Hardware-Software Co-Design to Accelerate Irregular Applications in the Post-Moore’s Law Era" on Wednesday, January 15, 2020 at 10am in CS 302
by Nicki Mahler 08 Jan '20

08 Jan '20

Aninda Manocha will present her General Exam, "Hardware-Software Co-Design to Accelerate Irregular Applications in the Post-Moore’s Law Era" on Wednesday, January 15, 2020 at 10am in CS 302. The members of her committee are as follows: Margaret Martonosi (adviser), David Wentzlaff, and David August Everyone is invited to attend her talk, and those faculty wishing to remain for the oral exam following are welcome to do so. Her abstract and reading list follow below. Despite their ubiquity … [View More]in many important real-world, big-data applications, graph and other sparse applications remain difficult to accelerate even with modern accelerator-oriented, heterogeneous system designs. Many of these applications are characterized by irregular memory accesses caused by pointer indirection, which confounds caching mechanisms that hinge on the notion of locality as well as traditional prefetching and speculation techniques. As a result, these applications are bottlenecked by several long-latency memory accesses. First, my work approaches these workloads from a latency-tolerance perspective by proposing a Decoupled Access/Execute (DAE)-inspired technique, FAST-LLAMAs. This approach slices programs into Producer/Consumer threads and maps them onto simple in-order cores. Significant Memory-Level Parallelism (MLP) is then achieved in the form of dependency-free loads and asynchronous read-modify-write (RMWs) instructions issued on the Producer whose data is efficiently read by the Consumer. By using full-stack innovations in a simple, in-order, multi-core architecture, FAST-LLAMAs transforms long-latency memory accesses into requests that can issue asynchronously, thus hiding the cost of many costly accesses. With a single Producer/Consumer pair, FAST-LLAMAs yields a geomean of 4.21x and up to an 8.66x speedup over a single in-order core. Under the same area budget, the simple in-order cores of FAST-LLAMAs achieve a geomean of 11.79x and up to a 20.8x improvement in energy efficiency over out-of-order cores without requiring application-specific hardware. In order to address memory bandwidth limits of these irregular applications, my work then proposes reconfigurable, intelligent caching techniques called GSC (Graph-Specialized Caching) that optimize for separately allocated regions of memory employed in such applications. By isolating and specializing caching policies for the irregular memory accesses of such workloads, GSC techniques mimic a customized memory hierarchy with reconfigurability. More specifically, they employ logical cache partitioning, tailored access granularities, and node degree-based replacement policies to target irregular memory accesses. As a result, GSC techniques achieve a geomean of 1.70x and up to a 2.54x speedup, a geomean of 3.76x and up to 12.76x improvements in energy efficiency, and a geomean of 3.29x and up to a 4.74x improvement in bandwidth savings. This allows for parallel scaling far beyond what prior state-of-the-art memory hierarchies have achieved. Reading List James E. Smith. “Decoupled access/execute computer architectures.” In Proceedings of the 9th International Symposium on Computer Architecture (ISCA), pages 112-119. IEEE Press, 1982. James R. Goodman. “Using cache memory to reduce processor-memory traffic.” In Proceedings of the 10th International Symposium on Computer Architecture (ISCA), pages 124–131. ACM, 1983. Guilherme Ottoni, Ram Rangan, Adam Stoler, and David I. August, “Automatic thread extraction with decoupled software pipelining,” in Proceedings of the 38th International Symposium on Microarchitecture (MICRO), pages 107–118. IEEE Press, 2005. Mattan Erez, Jung Ho Ahn, Jayanth Gummaraju, Mendel Rosenblum, and William J. Dally. “Executing irregular scientific applications on stream architectures.” In Proceedings of the 21st International Conference on Supercomputing (ICS), pages 93–104. ACM, 2007. Carole-Jean Wu, Aamer Jaleel, Will Hasenplaugh, Margaret Martonosi, Simon C. Steely, Jr., and Joel Emer, “SHiP: Signature-based hit predictor for high performance caching.” In Proceedings of the 44th International Symposium on Microarchitecture (MICRO), pages 430–441. ACM, 2011. Tae Jun Ham, Juan L. Aragón, and Margaret Martonosi. “DeSC: Decoupled supply-compute communication management for heterogeneous architectures.” In Proceedings of the 48th International Symposium on Microarchitecture (MICRO), pages 191–203. ACM, 2015. Tae Jun Ham, Lisa Wu, Narayanan Sundaram, Nadathur Satish, and Margaret Martonosi. “Graphicionado: A high-performance and energy-efficient accelerator for graph analytics.” In Proceedings of the 49th International Symposium on Microarchitecture (MICRO), pages 1–13. IEEE Press, 2016. Sam Ainsworth and Timothy M. Jones. “An event-triggered programmable prefetcher for irregular workloads.” In Proceedings of the 23rd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 578–592. ACM, 2018. Abanti Basak, Shuangchen Li, Xing Hu, Sang Min Oh, Xinfeng Xie, Li Zhao, Xiaowei Jiang, and Yuan Xie. “Analysis and optimization of the memory hierarchy for graph processing workloads.” In Proceedings of the 2019 International Symposium on High Performance Computer Architecture (HPCA), pages 373–386. IEEE Press, 2019. Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Crago, Kartik Hegde, Rangharajan Venkatesan, Steven W. Keckler, Christopher W. Fletcher, and Joel Emer, “Buffets: An efficient and composable storage idiom for explicit decoupled data orchestration,” in Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 137-151. ACM, 2019. Textbook: John L. Hennessy and David A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann 5th edition (2011). [View Less]

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Zachary Teed will present his General Exam, "Video to Depth with Differentiable Structure from Motion" on Tuesday, January 14, 2020 at 4pm in CS 401
by Nicki Mahler 07 Jan '20

07 Jan '20

Zachary Teed will present his General Exam, "Video to Depth with Differentiable Structure from Motion" on Tuesday, January 14, 2020 at 4pm in CS 401. The members of his committee are Jia Deng (adviser), Olga Russakovsky, and Szymon Rusinkiewicz. Everyone is invited to attend his talk, and those faculty wishing to remain for the oral exam following are welcome to do so. His abstract and reading list follow below. Title: Video to Depth with Differentiable Structure from Motion Abstract: … [View More]In video to depth, the task is to estimate depth from a video sequence. This problem has traditionally been approached using Structure from Motion (SfM), which takes a collection of images as input, and jointly optimizes over 3D structure and camera motion. In parallel, deep learning has been highly successful on a number of 3D reconstruction tasks, but as recent work has shown, it is often hard to train generic network layers to directly utilize multiview geometry. We propose an end-to-end learning architecture for predicting depth from video which combines the representation ability of neural networks with the geometric principles governing image formation. We compose a collection of classical geometric algorithms, which are converted into trainable modules and combined into an end-to-end differentiable architecture. We evaluate our approach on 5 separate datasets, and outperform all existing single-view or multi-view approaches, while also demonstrating that our method can generalize across datasets. Textbook: Szeliski, Richard. Computer vision: algorithms and applications. Springer Science & Business Media, 2010. Papers: Engel, Jakob, Thomas Schöps, and Daniel Cremers. "LSD-SLAM: Large-scale direct monocular SLAM." European conference on computer vision. Springer, Cham, 2014. Engel, Jakob, Vladlen Koltun, and Daniel Cremers. "Direct sparse odometry." IEEE transactions on pattern analysis and machine intelligence 40.3 (2017): 611-625. Kümmerle, Rainer, et al. "g 2 o: A general framework for graph optimization." 2011 IEEE International Conference on Robotics and Automation. IEEE, 2011. Ranftl, Rene, et al. "Dense monocular depth estimation in complex dynamic scenes." Proceedings of the IEEE conference on computer vision and pattern recognition. 2016. Schonberger, Johannes L., and Jan-Michael Frahm. "Structure-from-motion revisited." Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition. 2016. Quiroga, Julian, et al. "Dense semi-rigid scene flow estimation from rgbd images." European Conference on Computer Vision. Springer, Cham, 2014. Amos, Brandon, and J. Zico Kolter. "Optnet: Differentiable optimization as a layer in neural networks." Proceedings of the 34th International Conference on Machine Learning-Volume 70. JMLR. org, 2017. Dosovitskiy, Alexey, et al. "Flownet: Learning optical flow with convolutional networks." Proceedings of the IEEE international conference on computer vision. 2015. Kendall, Alex, et al. "End-to-end learning of geometry and context for deep stereo regression." Proceedings of the IEEE International Conference on Computer Vision. 2017. Tang, Chengzhou, and Ping Tan. "Ba-net: Dense bundle adjustment network." arXiv preprint arXiv:1806.04807 (2018). Zhou, Huizhong, Benjamin Ummenhofer, and Thomas Brox. "Deeptam: Deep tracking and mapping." Proceedings of the European Conference on Computer Vision (ECCV). 2018. [View Less]

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Zoe Paraskevopoulou will present her pre-FPO "An Verified Optimizing Backend for a Purely Functional Language" on January 14, 2020 in CS 402 at 10am
by Nicki Mahler 06 Jan '20

06 Jan '20

Zoe Paraskevopoulou will present her pre-FPO "An Verified Optimizing Backend for a Purely Functional Language" on January 14, 2020 in CS 402 at 10am. The members of her committee are: Andrew Appel (adviser), David Walker (reader), Amal Ahmed (Northeastern University), Aarti Gupta (non-reader), Zachary Kincaid (non-reader) Everyone is invited to attend her talk. The talk title and abstract follow below. An Verified Optimizing Backend for a Purely Functional Language --------------------… [View More]------------------------------------------------------------------------------------- CertiCoq is a verified compiler for the source language of the interactive theorem prover Coq. The goal of CertiCoq is to bridge the gap between a certified source program and the compiled executable program. Coq's source language, Gallina, is a pure functional language without side effects. To allow programs to interact with their environment despite the lack of side effects, CertiCoq compiles Gallina to C, where the program can be linked with C code that handles the input and the output. In my thesis, I focus on the design, the implementation, and the verification of the optimizing backend of CertiCoq, that is responsible to efficiently compile untyped higher-order functional code to a first-order representation ready to be complied to C. The design of the CertiCoq backend follows a micropass compiler architecture that consists of small compiler passes each of them performing a simple task, and optimizations in the final code rely on the interaction of these transformations. To prove the set of backend transformations correct, I developed a proof framework based on step-indexed logical relations, a powerful proof technique that is used to show program equivalence. The modular and compositional nature of logical relations greatly fits the architecture of our compiler, allowing for proof reuse and compositional reasoning. Despite their mathematical elegance, logical relations cannot generally be used to show correctness of separate compilation in multi-pass compilers. I show how our existing proof framework can be extended to provide guarantees not only about whole-program compilation, but also about the correctness of the interaction of programs that are compiled separately through CertiCoq, perhaps using different backend optimizations. This is the first time that logical relations are used to obtain a proof of correctness for separate compilation. In the second part of my thesis, I show how to strengthen the guarantees that the proof framework provides, but from a different angle. Bugs in compilers manifest themselves not only in the final result of the computation, what we usually call functional correctness of the transformation, but also in other observable behaviours of the program, such as resource consumption. In order to ensure that a transformation will not introduce timing and memory leaks, I extended the logical relation framework so that it supports reasoning about preservation of running time and space. I used this extended proof framework to prove that the closure conversion algorithm of CertiCoq is not only correct with respect to the final result, but also safe for space. Furthermore, I also show that the garbage collection strategy followed by CertiCoq is safe with respect to the idealistic space consumption model. This is the first formal proof of space-safety for a closure conversion algorithm and a particular garbage collection strategy and also the first time that logical relations were used to reason about space safety. [View Less]

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