Prakash Murali will present his Pre FPO "Enabling Practical Quantum Computation: Compiler and Architecture Techniques for Bridging the Algorithms-to-Devices Resource Gap" on Thursday, December 17, 2020 at 9am via Zoom.
Committee: Margaret Martonosi (Advisor, Reader, Examiner); Readers: Kyle Jamieson and Fred Chong (University of Chicago); Examiners: Andrew Houck (Princeton EE), Nathalie de Leon (Princeton EE)
Title: Enabling Practical Quantum Computation: Compiler and Architecture Techniques for Bridging the Algorithms-to-Devices Resource Gap
Abstract: Quantum computing (QC) is a radically new paradigm which is poised to impact diverse fields such as cryptography, chemistry and machine learning. In recent years, QC hardware has progressed considerably with small systems being prototyped by industry and academic vendors. However, there is a huge gap between the resource requirements of promising applications and the hardware that is buildable now; qubit counts and operational noise constraints of applications exceed hardware capabilities by 5-6 orders of magnitude. My thesis seeks to enable practical QC by bridging this gap: from the top with novel compiler techniques to optimize application requirements and from the bottom via system architectures efficiently exploiting scarce QC resources.
Towards bridging the gap from the top, my thesis proposes two techniques: noise adaptive compilation to adapt application executables to the variable noise characteristics of QC devices and software approaches for mitigating crosstalk errors which occur during parallel gate operations. On real QC executions, we demonstrate average fidelity improvements of 3X using noise-adaptivity and 2X using crosstalk mitigation, compared to state-of-the-art techniques. Towards closing the gap from the bottom, my work includes extensive architectural analysis for current superconducting and trapped ion-based QC systems and hardware-software co-design techniques to improve the fidelity of next-generation trapped ion systems. In response to my work, several industry vendors have included noise-adaptivity and its extensions as part of their toolflows and adjusted device architecture to expose more native operations and hardware characterization data.