Nayana Prasad Nagendra will present her FPO "IMPROVING INSTRUCTION CACHE PERFORMANCE FOR MODERN PROCESSORS WITH GROWING WORKLOADS" on Wednesday, June 30, 2021 at 10AM via Zoom.

Zoom link: https://princeton.zoom.us/j/92249108132

The members of her committee are as follows:

David August (Adviser); Readers: David August and Tipp Moseley (Google); Examiners: David August, David Wentzlaff, Sharad Malik.

A copy of her thesis is available upon request. Please email gradinfo@cs.princeton.edu if you would like a copy of the thesis.

Everyone is invited to attend the talk.

Abstract follows below:

The performance of warehouse-scale computing has a considerable financial and environmental impact. Our work with Google shows that more than two-thirds of the CPU cycles are wasted even after the extensive optimizations used today.  Of these wasted cycles, nearly 20% are due to the processor front-end. In the first part of this talk, I will present the details of our fleet-wide study of Google workloads, a study we believe to be the first to explore front-end behavior at the warehouse scale. In the second part of this talk, I will present EMISSARY, a new instruction cache replacement algorithm designed to reduce these observed front-end stalls.  By exploiting the fact that not all cache misses cause stalls, EMISSARY reserves cache capacity for lines whose misses cause the most performance impact. EMISSARY outperforms all known cache replacement algorithms in both performance and energy consumption. In some cases, it produces speedups that exceed Belady's OPT, the perfect-knowledge minimal miss ideal cache replacement algorithm.