Caroline Trippel will present her Generals on May 12, 2015 at 10am in CS 301. The members of her committee are Margaret Martonosi (adviser), Andrew Appel, and David August. Everyone is invited to attend her talk, and those faculty wishing to remain for the oral exam following are welcome to do so. Her abstract and reading list follow below. Title: Accurate and Precise Translation and Compilation in the Face of Varying Memory Consistency Models Abstract Architecture-level heterogeneity is increasing: numerous products and studies have proven the benefits of combining cores and accelerators with varying ISAs into a single system. However, an underappreciated barrier to unlocking heterogeneity’s full potential is that the wide range of memory consistency models (MCMs) make it difficult to reason about differences in MCMs, and this in turn raises challenges in verifying or translating between them. My talk will discuss ArMOR (Architecture-independent Memory Ordering Requirements), a framework for specifying, comparing, and translating between MCMs. As a concrete example using this framework, my work aims to enable translation between MCMs without dramatically modifying hardware or recompiling code. I have used the Pin dynamic binary translation (DBT) infrastructure to create tools that enable code expecting “strong” hardware to be migrated to “weaker” hardware. My work has also explored workload characteristics that affect the performance overhead of this operation. Furthermore, I have looked at static translation from “weak” MCMs to “strong” MCMs, specifically studying late-stage translation of Android applications to x86 hardware. Reading List 1. Hans-J. Boehm and Sarita V. Adve. 2008. Foundations of the C++ concurrency memory model. In Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation (PLDI '08). ACM, New York, NY, USA, 68-78. DOI=10.1145/1375581.1375591 http://doi.acm.org/10.1145/1375581.1375591 2. Matthew DeVuyst, Ashish Venkat, and Dean M. Tullsen. 2012. Execution migration in a heterogeneous-ISA chip multiprocessor. In Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems(ASPLOS XVII). ACM, New York, NY, USA, 261-272. DOI=10.1145/2150976.2151004 http://doi.acm.org/10.1145/2150976.2151004 3. John L. Hennessy and David A. Patterson. 2003. Computer Architecture: A Quantitative Approach(3 ed.). Morgan Kaufmann Publishers Inc., San Francisco, CA, USA. 4. L. Lamport. 1979. How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs. IEEE Trans. Comput. 28, 9 (September 1979), 690-691. DOI=10.1109/TC.1979.1675439 http://dx.doi.org/10.1109/TC.1979.1675439 5. Daniel Lustig, Michael Pellauer, and Margaret Martonosi, “PipeCheck: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models”, 47th International Symposium on Microarchitecture (MICRO), Cambridge, UK, December 2014. 6. Daniel Lustig, Caroline Trippel, Michael Pellauer, and Margaret Martonosi. 2015. ArMOR: Defending Against Memory Consistency Model Mismatches in Heterogeneous Architectures. In Proceedings of the 42nd Annual International Symposium on Computer Architecture (ISCA '15). Portland, OR, June 2015. 7. Abhayendra Singh, Satish Narayanasamy, Daniel Marino, Todd Millstein, and Madanlal Musuvathi. 2012. End-to-end sequential consistency. In Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA '12). IEEE Computer Society, Washington, DC, USA, 524-535. 8. Daniel J. Sorin, Mark D. Hill, and David A. Wood. 2011. A Primer on Memory Consistency and Cache Coherence (1st ed.). Morgan & Claypool Publishers. 9. Ashish Venkat and Dean M. Tullsen. 2014. Harnessing ISA diversity: design of a heterogeneous-ISA chip multiprocessor. In Proceeding of the 41st annual international symposium on Computer architecuture (ISCA '14). IEEE Press, Piscataway, NJ, USA, 121-132.