UART interrupts

[Ananthanarayanan, Arul]

Perry,
	On the B step the CoProcessor 15 ID_CHIP command will return a 1 in
bit 0. If you
read a 0, you have the A step.

You have the old cdrom. You need to get the new 1.0 version (1.0.1129) as it
has the specification
update that lists all the differences between the steps. You should be able
to get this
from your Intel support person.

Arul

-----Original Message-----
From: Perry Wagle [mailto:wagle at cse.ogi.edu]
Sent: Tuesday, July 11, 2000 3:36 PM
To: arul.ananthanarayanan at intel.com; ixp1200 at CS.Princeton.EDU;
wagle at cse.ogi.edu
Subject: RE: UART interrupts


Arul --

How do I tell for sure whether I have an A or B step IXP1200?  The
Coprocessor 15 (MMU) ID_CHIP command (section 4.10.1) returns
0x6901c120, which means revision 0 of something (the MMU?).  The edge
of the board near the serial connector says "A13033-001 A01 L1" on the
side with most of the chips, and "A13033 001 A01 L8" on the other
side.

What are all the differences between Rev A and Rev B?  If the
documentation I have is going to be this far off in general, I'm not
sure I can port Linux to the board, and I need to complain.

Which document on the Version 1.0.1011 CDrom (that came with the
boards) are you talking about that describes the uart?

---

I thought I'd tried setting mystery bit 9 to see if it would clear the 
interupt.  It seems to work now.  You have to reinitialize the uart
(setting baud, etc) after each interupt?

Thanks!

-- Perry

> From arul.ananthanarayanan at intel.com  Tue Jul 11 14:34:53 2000
> From: "Ananthanarayanan, Arul" <arul.ananthanarayanan at intel.com>
> To: "'Perry Wagle'" <wagle at cse.ogi.edu>, ixp1200 at CS.Princeton.EDU
> Subject: RE: UART interrupts
> Date: Tue, 11 Jul 2000 14:34:47 -0700
> MIME-Version: 1.0

> Perry,
> > The documentation refers to the B stepping of the IXP1200. You
> probably have
> the A step of the processor and there are differences in handling the
UART.

> In the A stepping, bit 6 of the IRQ register is really the UART interrupt
> (not the RTC).

> You do need to clear the UART interrupts on the A step, so the mystery bit
9
> of the
> UART_SR is what you need to set before exiting your handler.

> There is a specification update on the Version 1.0 developers CD that
> details the changes
> for the A step.

> Arul

> -----Original Message-----
> From: Perry Wagle [mailto:wagle at cse.ogi.edu]
> Sent: Monday, July 10, 2000 5:22 PM
> To: ixp1200 at CS.Princeton.EDU
> Subject: UART interupts


> Has anyone gotten the UART interupts to work right?

> I can read and write the UART just fine with polled i/o, but
> interupts seem all messed up.  I suspect the March 2000 IXP1200
> Network Processor Programmer's Reference is either false or I wasn't
> given the board that it corresponds to.

> Section 4.6.10 UART_CR (page 4-78): The UART generates a IRQ interupt
> regardless of what I set set bit 9 (UIS, select IRQ or FIQ) to.
> Setting bit 4 (RIE) is necessary to get IRQ interupts to fire, but
> once I get them to fire, they won't stop firing.  My IRQ handler will
> be entered even if there are no characters ready to read from the UART
> after I've left it for the first time.  It won't enter my IRQ_handler
> the first time until I've send a character.  If I read the UART_CR
> register, I get what I set it to except for UIS is always zero; ie,
> 0x001700f0 (9600baud, the mystery bit 9 (UIS) is clear, transmit
> interupts disabled, uart enabled, 8 bits data size, recieve interupts
> enabled, 1 stop bit, no parity).

> What is the mystery bit 9?

> Section 4.6.9 UART_SR (page 4-77): This register address is always [?]
> equal to "RXD pin set, transmit fifo full, ... , transmit fifo empty,
> ..." (0x00000180) when my IRQ_handler is entered (except the first
> time, when the "receive fifo ready" bit is also set (0x00000190)).

> It would seem impossible that the transmit fifo is both full and empty 
> at the same time, what's going on?

> Section 4.6.17 IRQ (page 4-86): When my IRQ_handler is entered, this
> register is always equal to "IRQ interupt generated by RTC" (bit 6 =
> 0x00000040), and no matter what I do to the UART status, control, and
> data registers, its still set when my IRQ_handler is ready to leave
> (ie, after its read one character after waiting for it to become
> available).  I suspect that since I'm not succeeding in clearing the
> interupt condition, that its being reissued just as soon as I leave
> the interupt handler.

> I'm thinking that bit 6 corresponds to the UART, and not the RTC,
> since my IRQ handler is only entered for the first time when I send a
> character to the IXP1200 serial port.  I have apparently not succeeded
> (yet) in getting the RTC to generate an interupt.  What is the correct 
> layout of the IRQ register?

> My foreground job (spin the led with an ever-incrementing unsigned
> char counter in a tight infinite loop) usually doesn't make progress
> after my IRQ_handler is entered for the first time.  But when it does,
> it has only 2-3 "favorite" values that the led ends up displaying.  It
> seems odd that I've got such a good phase lock on 2-3 out of 256
> possible values, but I can't imagine what this information is telling
> me.

> -- Perry