Loading MicroEngine code
Paige, Dale W
dale.w.paige at intel.com
Thu Jun 8 18:28:32 EDT 2000
What OS are you running?
Are you certain that the SA core is treating data accesses to the CSR range
data as non-cacheable and non-bufferable?
-----Original Message-----
From: Tammo Spalink [mailto:tspalink at CS.Princeton.EDU]
Sent: Thursday, June 08, 2000 2:09 PM
To: ixp1200 at CS.Princeton.EDU
Subject: Re: Loading MicroEngine code
No effect I am afraid.
Tammo
On Thu, 8 Jun 2000, "Paige, Dale W" wrote:
> Tammo -
>
> Try writting the address again prior to the read.
>
> csrWrite(CSR, USTORE_ADDR, addr); // Set the target address
> csrWrite(CSR, USTORE_DATA, 0xD8100020); // Write an instruction
> csrWrite(CSR, USTORE_ADDR, addr); // Set the target address
AGAIN
> <==
> result = csrRead(CSR, USTORE_DATA);
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