[ixp1200] Microcode question...

[Austen McDonald]

	Attached is bounce.uc and init.h which should receive a 64byte
packet from MAC 1 port 0 (gigabit) and send it right back out (it doesnt
change the addresses or anything). It doesnt work. Apparently,
ctx_arb[start_receive] never returns which means that the recv request
never completes or is formatted improperly. Im running bounce.list on uE 0
so Im having the IX bus signal thread 0.

	If you run it, my seven-segment-display says A1 meaning that it
hasnt gotten back form the ctx_arb yet. If it says A2 its gotten back. The
other status symbols are in bounce.uc.

	Id appreciate any help, thanks,

Austen McDonald
austen at cc.gatech.edu

God does not care about our mathematical difficulties. 
He integrates empirically.
  -- Albert Einstein
-------------- next part --------------
/* bounce.uc
 * Recv packet on MAC1 port 0 then transmit packet using MAC 1 port 0
 */
br!=ctx[0,killit#]

.xfer_order $$x0,$$x1,$$x2,$$x3,$$x4,$$x5,$$x6,$$x7
.xfer_order $x0,$x1,$x2,$x3

immed_w0[ledaddr,0x2000]
immed_w1[ledaddr,0x74]

immed[$x2,0xff]
sram[write,$x2,ledaddr,0,1],ctx_swap
#include "../init.h"

loop#:
/* receive loop */
waitloop#:	
	csr[read,$x0,rcv_rdy_cnt]
	alu_shf[$x2,--,B,$x0,>>24]
	sram[write,$x2,ledaddr,0,1],ctx_swap
	alu_shf[--,1,AND,$x0,>>24] /* check fast port ready #1 */
	br=0[waitloop#]

immed[$x2,0xa0]
sram[write,$x2,ledaddr,0,1],ctx_swap
notready#:
	br_inp_state[rec_req_avail,okready#]
	br[notready#]

okready#:
	immed[$x2,0xa1]
	sram[write,$x2,ledaddr,0,1],ctx_swap
	immed_w0[gpr0,0x8] /* mac 1: port 0, signal thread 0 */
	immed_w1[gpr0,0x1] /* fast port mode, sequence 1, fifo #1=0, fifo #2=1 */
	alu[$x1,--,B,gpr0]
	csr[write,$x1,rcv_req],ctx_swap ; write to RCV_REQ and block until done
	ctx_arb[start_receive] ; wait for receive signal from IX Bus
	csr[read,$x1,rcv_cntl] ; read RCV_CNTL to clear RCV_CNTL FIFO
	immed[$x2,0xa2]
	sram[write,$x2,ledaddr,0,1],ctx_swap

	; ok, data is in RFIFO, let's get it out and put it in SDRAM
	immed[gpr0,0,0] ; we'll use this as the dest addr ie put data at
	                ;base of SDRAM

	; indirect value for sdram instruction: read the number of quadwords
	; from RCV_CNTL
	immed[gpr1,7,0] ; read 8 - 1 quadwords
	alu_shf[--,--,B,gpr1,<<16]
	; read into sdram, note that the 8 on the end is simply ignored;
	; it's replaced by the indirect value
	sdram[r_fifo_rd,--,0,gpr0,8],indirect_ref,ctx_swap

	/* transmit */

	/* fill tfifo */
	/* decide which element to place data in */
	csr[read,$x0,xmit_ptr],ctx_swap /* $x0 is now element number */
	alu[$x0,0xf,AND,$x0] /* clear reserved area */

	/* form indirect reference for sdram, put it in gpr0 */
	alu_shf[gpr0,--,B,0x7,<<16]
	alu_shf[gpr0,gpr0,OR,$x0,<<4] /* gpr0 is the indirect ref for sdram */

	/* for indirect reference for fast_wr, put it in gpr1 */
	alu_shf[gpr1,--,B,$x0,<<5]
	alu_shf[gpr1,gpr1,OR,0x1,<<15]

	/* make gpr2 the addr of the control element then write control data */
	immed[gpr2,128]
	alu_shf[gpr2,gpr2,+,$x0,<<1] /* add 2*element number */
	immed[$x0,0xff08] /* control data: 8 qw/8 bytes in last qw & EOP/SOP */
	immed[$x1,0]
	immed[$x2,0]
	immed[$x3,0]
	t_fifo_wr[$x0,gpr2,0,2],ctx_swap /* write control data */

	/* actually copy data */
	alu[--,--,B,gpr0]
	sdram[t_fifo_wr,--,0, addr,8],indirect_ref,ctx_swap

	immed[$x2,0xb0]
	sram[write,$x2,ledaddr,0,1],ctx_swap

	/* wait for ready to transmit */
	//rdywait#:
	//	csr[read,$x0,xmit_rdy_lo],ctx_swap
	//	alu[--,$x0,AND,0x1]
	//br!=0[rdywait#]

	immed[$x2,0xbb]
	sram[write,$x2,ledaddr,0,1],ctx_swap

	/* send it */
	alu[--,--,B,gpr1] /* the tfifo element to use */
	fast_wr[0,xmit_validate],indirect_ref

br[loop#]

killit#:
ctx_arb[kill]
-------------- next part --------------
/* init.h

 * init ready bus

 */



/* fast port mode: single thread mode 00

 * autopush prevent window = 3

 * autopush: rdycount and rdy_lo to regs, signal thread 4

 * autopush DISABLED!

 */

//immed[gpr0,0xaa4]

//immed[gpr0,0x0ca4]

immed[gpr0,0x4c00]

//immed[gpr0,0xee4]

alu[$x0,--,B,gpr0]

csr[write,$x0,rcv_rdy_ctl],ctx_swap

immed[$x0,0]

csr[write,$x0,xmit_rdy_ctl],ctx_swap

immed[$x0,0,0]

csr[write,$x0,fp_ready_wait],ctx_swap

immed[$x0,0x01]

csr[write,$x0,rdybus_synch_count_default],ctx_swap



/* ready bus program:

 * txrdy 0-1 (d7)

 * nop (1f)

 * rxrdy 0-1 (db)

 * nop (1f)

 */ 

immed_w0 [gpr0, 0x1fd7]

immed_w1 [gpr0, 0x1fdb]

alu [$x0, --, b, gpr0]

csr [write, $x0, rdybus_template_prog1]

csr [write, $x0, rdybus_template_prog2]

csr [write, $x0, rdybus_template_prog3],ctx_swap



/* enable rdy bus

 * 1-2 mac mode

 * 64 bit bidirectional ix bus

 * rdy bus master

 * macs dont return status

 * big endian

 */

immed_w0[gpr0,0xf40]

immed_w1[gpr0,0]

alu[$x0,--,B,gpr0]

csr[write,$x0,rdybus_template_ctl],ctx_swap