[ixp1200] Prefetch and Non-Prefetch SDRAM

[Scott C. Karlin]

On Wed, Nov 06, 2002 at 04:15:46AM -0700, Shyamal Pandya wrote:
> Hi,
> Could someone tell me the distinction between prefetch and non-prefetch 
> SDRAM on the IXP1200?

The prefetch and non-prefetch distinction only applies to the
StrongARM core.  For details see section 7.6.1 of the IXP1200
Hardware Reference Manual.  Basically, StrongARM core reads to
prefetch memory cause the next 8 longwords to automatically be
fetched (into cache) to reduce latency of future reads.

> And why does the resource manager provided with the 
> IXA Ace framework use only the uncached SDRAM?

I'm not familiar with the IXA Ace framework, but I would guess
that it is because the microengines do not have caches.

> While at it could someone tell me what is the cache flush area meant to be?

See section 3.2.4.5 of the IXP1200 Hardware Reference Manual.
Basically it is a special area of memory that always reads
as 0 without external memory latency.

Scott