[ixp1200] Call for Papers: IEEE Network Magazine -- special issue on Networ k Processors: Architectures, Tools and Applications

[Vin, HarrickX]

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                         CALL FOR PAPERS
              IEEE Network Magazine Special Issue on
    Network Processors: Architectures, Tools, and Applications

Guest Editors: 
   Raj Yavatkar                        Prof.  Harrick Vin          
   Intel Corporation                   Department of Computer Sciences
   2111 NE 25th Avenue, JF3-462        University of Texas at Austin
   Hillsboro, OR, 97124                Austin, TX 78712-1188
   raj.yavatkar at intel.com              vin at cs.utexas.edu
   Tel: (503) 264 9077                 Tel: (512) 471-9732

Scope:
The rapid and pervasive evolution of the Internet has created an insatiable
need for supporting sophisticated services and high bandwidth at both edges
of the network and within the network infrastructure. Traditionally, telecom
and datacom equipment vendors have used fixed-function ASICs to implement
packet-processing functions in hardware. However, such ASICs provide little
flexibility when the type or nature of the media interfaces change or new
protocol standards require changes to lookup operations or header
processing. To meet the demand for higher performance, flexibility, and
economy, an alternative to ASICs, called network processors (NPs), has
emerged. These processors are programmable and their designs are optimized
for processing packets; they can be used to implement efficiently a wide
range of network services such as IP datagram forwarding, label switching,
content-based routing, voice-over-packet, VPNs, and Quality of Service
(QoS). We use the term network processor here in a generic sense to
represent devices ranging from task-specific processors, such as
classification and encryption engines, to more general-purpose, programmable
packet or communications processors. Because many of these NPs are
programmable, they offer a significant advantage over ASICs as new features
or functions can be introduced or modified easily without having to
re-design a network component.  
 
Design and development of networking systems using network processors is an
emerging field that offers numerous challenges and opportunities. The goal
of this special issue is to publish contributions from both industry and
academia that describe the state-of-the-art in the architecture, design,
programming, software tools, and use of network processors. Papers with
tutorial/survey content are also welcome. Topics of particular interest
include (but are not limited to):
   *    Architectures for network processors  
   *    Novel product designs based on NPs 
   *    Co-processors for search/lookup, packet classification, compression,
        encryption and security, etc.
   *    Design and implementation of new techniques/algorithms for QoS,
        voice-over-packet, wireless communication, etc
   *    Programming languages, tools, and development environments for
        software development on NPs 
   *    Benchmarking and performance analysis 
   *    Interfaces to high-speed packet buses and switch fabrics 
   *    Techniques for accelerating network services 
   *    Performance measurement and analysis 
   *    Novel applications made possible by NPs

Submission Guidelines:
Interested authors should submit an electronic version of the manuscript
either in Postscript or PDF format as an email attachment to one of the
guest editors. Additional information including "Guidelines for authors" is
available at the IEEE Network Website:
http://www.comsoc.org/pubs/net/ntwrk/authors.html
 
Important Dates:
Paper Submission Deadline: October 30, 2002
Feedback to Authors: February 1, 2003
Final Manuscripts to Publisher: April 1, 2003
Publication of Special Issue: July 2003