[ixp1200] Control of microengines and threads++

[Øyvind Hvamstad]

On Thu, 2004-07-22 at 21:57, Johnson, Erik J wrote:
> Going strictly from memory, here is what I remember 

Hi, Mr. Johnson. Thanks for your reply. I have your book btw. :)

> 1) How are the microACEs distributed among the microengines when using a
> default configuration file? I am unable to find any documentation on
> this subject (The ixsys.* files are generally poorly documented :)).
> 
> The distribution is based on the number, speed, and direction of the
> interfaces.  For each 100Mb/s interface, two microengines are allocated
> for all microblocks marked as "receive side", and one microengine is
> allocated for all "transmit side" microblocks.  For every 4 10Mb/s
> interfaces, one microengine is allocate for the receive side and one
> microengine for the transmit side.

I do not understand this!

The chip has 6 µengines. If two µengines are allocated for the "receive
side" and 1 is allocated for the "transmitt side" per interface. Then, 3
µengines are needed per interface. Does that mean that 4 100Mb/s
interfaces will require 12 µengines?

Then you say that 10 Mb/s interfaces require 2 µes each, that means 8
µes?

Seems I'm short of a few µes, or more likely; I'm getting this all
wrong!

> 4) Does the IngressACE do any processing of packets, or does it only
> define the macros that I use in my dispatch loop? According to the
> design documents and the source the latter seems to be it, but I'd like
> to be 100% sure.
> 
> I guess it depends on your definition of "processing".  The ingress ACE
> core component does not process packets.  The ingress ACE microblock
> reassembles mpackets into a single packet and checks the destination MAC
> address of the packet to ensure the packet belongs to the system.

When you say ingress ACE microblock, do you in fact mean the
EthernetIngress macro? (e.g., SlowIngress macro).

> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Erik J. Johnson
> Intel Research & Development
> erik.j.johnson at intel.com
> NOT SPEAKING FOR INTEL
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- 
Øyvind Hvamstad <oyvindh at ifi.uio.no>