[ixp1200] chapter 8 ethernet header problem

[Vijay Ramamurthi]

Hi,
I think the hash error problem was discussed in an earlier thread.
I am not sure if its the same one
It is coming baecause there is a error in the ixp.h file,
the read and write registers have been interchanged.
There is a patch for the sdk version available from the
intel web site for free, which has this fix and a lot of  fixes.
If you have already put in the patch, just go thru the ixp.h file
and see to it that you match the write and read regsiters.
Still if you get a error you might be using a struct/union for the input
to the hash(write registers), whichll might cause it to read the write
registers, just declare a temp register (of the same struct) and copy that
to the write register.

Hope this helps
Vijay

On 8 Nov 2004, nitin  makhija wrote:

> Hellow,
> i'm not even able to debug the chapter 8 example, its giving error regard=
ing hash unit.......so can anyone send me the files for example code of cha=
pter 8....debug results are as follows::::
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> ........................................................
> D:\Study\Project_IXP\test_nitin\Chapter08\bridging-latency.c(158): error =
:  intrinsic data buffer "hashInput_103$1$0"=20
cannot be read
>  :=20
>  : bridging-latency.c
>  : buffer.c
>  : receive.c
>  : Reading debug file D:\Study\Project_IXP\test_nitin\Chapter08\bridging-=
latency.dbg
>  : Reading debug file D:\Study\Project_IXP\test_nitin\Chapter08\buffer.db=
g
>  : Reading debug file D:\Study\Project_IXP\test_nitin\Chapter08\receive.d=
bg
> Compiling for receive-bridge-enqueue-me1.list...
>  : Intel(r) Microengine C Compiler, Version 2.01 (2002/01/14 15:08:38)
>  : Copyright (C) 1985-2001 Intel Corporation.  All rights reserved.
>  :=20
>  : IPO: using IR in D:\Study\Project_IXP\test_nitin\Chapter08\bridging-la=
tency.obj
>  : IPO: using IR in D:\Study\Project_IXP\test_nitin\Chapter08\buffer.obj
>  : IPO: using IR in D:\Study\Project_IXP\test_nitin\Chapter08\receive.obj
>  : IPO: performing multi-file optimizations
> D:\Study\Project_IXP\test_nitin\Chapter08\bridging-latency.c(158): error =
:  intrinsic data buffer "hashInput_103$1$0"=20
cannot be read
>  :=20
>  : bridging-latency.c
>  : buffer.c
>  : receive.c
>  : Reading debug file D:\Study\Project_IXP\test_nitin\Chapter08\bridging-=
latency.dbg
>  : Reading debug file D:\Study\Project_IXP\test_nitin\Chapter08\buffer.db=
g
>  : Reading debug file D:\Study\Project_IXP\test_nitin\Chapter08\receive.d=
bg
>=20
> Build results: (2) errors, (0) warnings     [press F4 to select errors/wa=
rnings]
> .........................................................................=
=2E............................................................... =A0
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> and when i tried this code while removing hash unit functions......then i=
'm getting a buffer overflow error.......
> do reply soon if anyone knows?????
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> Thaxs in advance..
> Regards,
> Nitin
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>=20
> On Sat, 06 Nov 2004 Shweta Rao wrote :
> >Hi,
> >I was running the chapter 8 example on develper's workbench in simulatio=
n mode.
> >The packet with ethernet addresses 'cafebabe' and 'deadbeef' arrives
> >in sdram correctly but when the structure headerData in datawatch
> >shows the first word of the quadword '0000cafe' repeated over and over
> >again . it does not show the correct ethernet addresses.Can anyone
> >tell me what is the problem?
> >
> >thanks,
> >shweta
> >_______________________________________________
> >ixp1200 mailing list
> >ixp1200 at lists.cs.princeton.edu
> >https://lists.cs.princeton.edu/mailman/listinfo/ixp1200
>=20
> _______________________________________________
> ixp1200 mailing list
> ixp1200 at lists.cs.princeton.edu
> https://lists.cs.princeton.edu/mailman/listinfo/ixp1200
>=20
>=20