[parsec-users] benchmarks L1 behavior

Jim Dempsey jim at quickthreadprogramming.com
Tue Sep 21 17:59:06 EDT 2010


I wrote a non-technical paper (article) in a 5-part series
(http://software.intel.com/en-us/articles/superscalar-programming-101-matrix
-multiply-part-1/)
 
This compares the benefits of L1, L2 and L3 (socket/NUMA node) scheduling
using the QuickThread parallel programming toolkit.
 
Jim Dempsey
jim at quickthreadprogramming.com

  _____  

From: parsec-users-bounces at lists.cs.princeton.edu
[mailto:parsec-users-bounces at lists.cs.princeton.edu] On Behalf Of Gagan
Singh
Sent: Tuesday, September 21, 2010 1:06 PM
To: PARSEC Users
Subject: [parsec-users] benchmarks L1 behavior


Hi all,

I have found lot of papers on cache behavior and off chip traffic for parsec
benchmark. The most detailed one being the Technical Report TR-811-08. 

Now, I am interested in knowing strictly l2 behavior excluding the l1 cache.
An example of this would be if a benchmark has very high l1 hit rate,
optimizing l2 wont be beneficial. Can anybody point me to a paper which
treats different cache behavior differently?

Thanks,
Gagan

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