[talks] Colloquium-Tuesday, September 22
Michele J. Brown
mjbrown at CS.Princeton.EDU
Fri Sep 18 14:27:46 EDT 2009
*Distinguished Speaker
Ivan Sutherland*,
Portland State University
*
*Small Auditorium (105)
Computer Science Building
4:30 pm
*"Fleet, Infinity & Marina"*
This talk describes a radically different architecture for computing
called Fleet. Fleet accepts the limitations to computing imposed by
physics: moving data costs more energy, more delay, and more chip area
than the arithmetic and logical operations ordinarily called
"computing." Fleet puts the programmer firmly in charge of the most
costly resource: communication. Fleet treats arithmetic and logical
operations as side effects of where the programmer sends data.
Fleet achieves high performance through fine grain concurrency.
Everything Fleet does is concurrent at the lowest level; programmers who
wish sequential behavior must program it explicitly. Fleet presents a
stark contrast to today's multi-core machines in which programmers seek
concurrency in an inherently sequential environment.
The Fleet architecture uses a uniform switch fabric to simplify chip
design. A few thousand identical copies of a configurable interface will
connect a thousand or so repetitions of basic arithmetic, logical,
input-output, and storage units to the switch fabric. The uniform switch
fabric and the identical configurable interfaces will simplify many of
the hard parts of designing the computing elements themselves.
Both software and FPGA simulators of a Fleet system are available at UC
Berkeley. Berkeley students have written a variety of Fleet programs;
their work helped to define what the configurable interface between
computing and communication must do. A simple compiler configures both
source and destination to provide flow-controlled communication. We
expect work on a higher-level language for Fleet to appear soon as a
Berkeley PhD dissertation.
Last year we built a 90 nanometer TSMC test chip, called Infinity, at
Sun Microsystems. Infinity demonstrated the switch fabric running at
about 4 GHz. We now have a new test chip, called Marina, also in
90-nanometer TSMC sponsored by Sun. Marina shows correct operation of
the configurable switch fabric interface. Together Infinity and Marina
give us confidence to build a complete Fleet. We seek participation from
sponsors, computer scientists, and hardware designers.
*BIO:*
Ivan Sutherland is a Visiting Scientist at Portland State University
where he and Marly Roncken have recently established the "Asynchronous
Research Center" (ARC). The ARC occupies both physical and intellectual
space half way between the Computer Science (CS) and Electrical and
Computer Engineering (ECE) departments at the university. The ARC seeks
to free designers from the tyranny of the clock by developing better
tools and teaching methods for design of self-timed systems. Prior to
moving to Portland, Ivan spent 25 years as a Fellow at Sun Microsystems.
A 1959 graduate of Carnegie Tech, Ivan got his PhD at MIT in 1963 and
has taught at Harvard, The University of Utah, and Caltech. Ivan is a
member of the National Academy of Engineering and the National Academy
of Sciences.
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