[talks] IEEE SSCS Distinguished Lecture Series at Princeton - October 16, 2014 - E-Quad B205

[Nicole E. Wagenblast]

S ent on behalf of Prof. Kaushik Sengupta 



IEEE SSCS Lehigh/Princeton/Columbia Chapters Present 
Distinguished Lecture Colloquia, October 2014 



October 16, 2014, 1:30–2:45 pm 
On-Chip Voltage and Timing Diagnostic Circuits 
Frank O’Mahony, Intel 

Abstract: This talk introduces a set of practical and powerful techniques and circuits to observe and characterize on-die circuitry. Measuring voltage and timing information on the chip itself alleviates the bandwidth and noise limitations associated with bringing signals off-chip to be measured. Specific applications of these techniques include measurement and characterization of power supply noise, power delivery impedance, clock skew, phase interpolator linearity, I/O eye margins, waveform capture, RX voltage noise and hysteresis, and RX clock-data jitter. Because the measurements are fully integrated, the rest of the system can be automatically adapted based on these metrics in a stand-alone manner. Best of all, many of these techniques leverage existing circuitry and are highly digital. 



October 16, 2014, 3:00–4:15 p.m. 
Millimeter-wave and Terahertz Integrated Circuits in Silicon Technologies: Challenges and Solutions 
Prof. Payam Hedari, University of California Irvine 

Abstract: The vastly under-utilized spectrum across millimeter-wave (mm-wave) and terahertz (THz) bands has generated great deal of excitement to investigate futuristic systems for 10+ gigabit short-range wireless as well as wideband sensing/imaging applications. Simply put, the shorter wavelength associated with the mm-wave/THz band is appealing since the physical dimensions of the antenna and associated electronics are reduced in size, making it possible to design multi-antenna structures to achieve beamforming, spatial diversity and multiplexing. 

Owing to aggressive scaling in feature size and device fT/fmax, nanoscale (Bi)CMOS technology potentially enables integration of sophisticated systems at THz frequency range, once only be implemented in compound III-IV semiconductor technologies. 

This talk will give an overview of recent advances in designing silicon-based integrated circuits will be capable of operating close to the maximum operation limits of silicon-based transistors. The talk then will discuss in depth about two case studies designed in UCI’s Nanoscale Communication Integrated Circuits (NCIC) Labs; namely, the world’s highest fundamental frequency fully differential transceiver in CMOS at 210 GHz, and the world’s highest frequency PLL-based Synthesizer in Silicon at 300GHz with a wide tuning range. 



October 16, 2014, 4:30–5:45 p.m. 
Low-Power, High-Bandwidth, and Ultra-Small Memory Module Design 
Prof. R. Jacob Baker, University of Nevada, Las Vegas 

Abstract: This work proposes a novel DRAM module and interconnect architectures in an attempt to improve computing energy use and performance. A low cost advanced packaging technology is used to propose an 8 die and 32-die memory module. The 32-die memory module measures less than 2 cm3. The size and packaging technique allow the memory module to consume less power than conventional module designs. A 4 Gb DRAM architecture utilizing 64 data pins is proposed. The DRAM architecture is inline with ITRS roadmaps and can consume 50% less power while increasing bandwidth by 100%. The large number of data pins are supported by a low power capacitive-coupled interconnect. The receivers developed for the capacitive interface were fabricated in 0.5 μm and 65 nm CMOS technologies. The 0.5 μm design operated at 200 Mbps, used a coupling capacitor of 100 fF, and consumed less than 3 pJ/bit of energy. The 65 nm design operated at 4 Gbps, used a coupling capacitor of 15 fF, and consumed less than 15 fJ/bit and order of magnitude smaller consumptions than previously reported receiver designs. 



Contact Info: Nagi Naganathan, nagisub at gmail.com or Kaushik Sengupta, kaushiks at princeton.edu 



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