[talks] Fwd: Seminar: Prof. Vijay Nagarajan, U Edinburgh. Dec 12: 4:30pm. CS 402.
mrm at princeton.edu
Mon Dec 12 10:03:51 EST 2016
Prof. Vijay Nagarajan from U. Edinburgh is visiting today and giving a computer architecture seminar at 4:30 in CS 402. The details are below. His one-on-one schedule is pretty full at this point, but please let me know if you’d like to be added.
> Monday Dec 12. 4:30pm. CS 402.
> Title: Semantics-directed Hardware Design for Shared Memory
> With regard to hardware support for shared-memory concurrency, an
> inherent trade-off between programmability and efficiency is presumed.
> For instance, the most intuitive memory consistency model, sequential
> consistency (SC), is presumed to be too expensive to support;
> likewise primitive synchronization instructions such as memory fences
> and atomic read-modify writes (RMWs) are costly in current processors;
> finally, there are question marks about whether cache coherence
> protocols will scale with increasing number of cores.
> In this talk, I will argue that it is indeed possible to provide
> hardware support that enhances programmability without sacrificing
> efficiency. The key insight is semantics-directed design: hardware
> design should be guided by precise formal specifications, instead of
> ad-hoc informal ones.
> I will illustrate this idea briefly by first showing how SC can be
> enforced efficiently using a novel technique to enforce memory
> ordering dubbed conflict ordering. Second, I will show how RMWs can be
> implemented efficiently in x86 architectures. Third, and the focus of
> this talk will be a scalable approach for cache coherence called
> TSO-CC. TSO-CC is a protocol that breaks the traditional
> coherence/consistency abstraction, relying on self-invalidation and
> acquire detection to satisfy the TSO memory consistency model. After
> briefly discussing the verification challenges that ensue, I will
> conclude with how I believe semanticists, hardware designers, and
> verification experts can work together to create correct and efficient
> hardware designs.
> Vijay Nagarajan is an Associate Professor at the University of
> Edinburgh. His research interests span computer architecture,
> compilers, and systems with a focus on memory consistency models and
> cache coherence protocols. Vijay received his PhD from University of
> California Riverside and MS from University of Arizona. He is a
> recipient of Intel Early Career Faculty Award and a best-paper award
> at PACT.
> Margaret Martonosi
> H. T. Adams '35 Professor of Computer Science.
> Princeton University ■ mrm at princeton.edu ■ http://www.princeton.edu/~mrm
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