[talks] Hansen Zhang will be presenting his general exam on Monday, May 9, 2016 at 1pm in CS 402.

[Nicki Gotsis]

Hansen Zhang will be presenting his general exam on Monday, May 9,2016 at 1pm in CS 402.

The members of his committee are David August (adviser), David Wentzlaff and Arvind Narayanan.

Everyone is invited to attend his talk, and those faculty wishing to remain for the oral exam following are welcome to do so.  His abstract and reading list follow below.

Abstract:
The TrustGuard architecture prevents the leakage of users’ information in the presence of malicious system components (processor and memory). The basis of trust in the system is a pluggable hardware element called the Sentry which physically separates the untrusted components and the interface to the outside world. To gain access to the external interfaces of the system, the untrusted components have to prove to the Sentry that their intended communication results from the correct execution of trusted software. This work improves upon the original TrustGuard design in two ways. First, it introduces optimizations that reduce the bandwidth requirements between the untrusted processor and the Sentry. Second, it adds protection from replay attacks to the original TrustGuard design. Simulation results show that the new design is able to reduce bandwidth by 60% while maintaining the performance of the original design and add protection from replay attacks.


Reading List:
Textbooks:
John L. Hennessy and David A. Patterson. 2011. Computer Architecture, Fifth Edition: A Quantitative Approach (5th ed.). Morgan Kaufmann Publishers Inc., San Francisco, CA, USA. 

Ross J. Anderson. 2008. Security Engineering: A Guide to Building Dependable Distributed Systems (2 ed.). Wiley Publishing. 
Chapter 3,4,5,11,16

Papers:
1, Secure processors/coprocessors
[1] G.E. Suh, D Clarke, B. Gassend, M. van Dijk, S. Devadas. AEGIS: architecture for tamper-evident and tamper-resistant processing. In Proceedings of the 17th annual international conference on Supercomputing, ICS’03, pages 160-171

[2] D. Y. Deng, D. Lo, G. Malysa, S. Schneider and G. E. Suh, "Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric," Microarchitecture (MICRO), 2010 43rd Annual IEEE/ACM International Symposium on, Atlanta, GA, 2010, pp. 137-148.

[3] R. Kannavara and N. G. Bourbakis, "Surveying secure processors," in IEEE Potentials, vol. 28, no. 1, pp. 28-34, January-February 2009.

[4] T. M. Austin, "DIVA: a reliable substrate for deep submicron microarchitecture design," Microarchitecture, 1999. MICRO-32. Proceedings. 32nd Annual International Symposium on, Haifa, 1999, pp. 196-207.

2, High Performance Caching
[5] M. K. Qureshi, A. Jaleel, Y. N. Patt, S. C. Steely, and J. Emer. Adaptive insertion policies for high performance caching. In Proceedings of the 34th annual international symposium on Computer architecture (ISCA '07). ACM, New York, NY, USA, 381-391

[6] A. Jaleel, K. B. Theobald, S. C. Steely, Jr., and J. Emer. High performance cache replacement using re-reference interval prediction (RRIP). In Proceedings of the 37th annual international symposium on Computer architecture (ISCA '10). ACM, New York, NY, USA, 60-71

3, Compression
[7] M. Thuresson, L. Spracklen and P. Stenstrom, "Memory-Link Compression Schemes: A Value Locality Perspective," in IEEE Transactions on Computers, vol. 57, no. 7, pp. 916-927, July 2008.

[8] X. Chen, L. Yang, R. Dick, L. Shang and H. Lekatsas, "C-Pack: A High-Performance Microprocessor Cache Compression Algorithm," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 8, pp. 1196-1208, Aug. 2010.


4, Memory Integrity Verification
[9] B. Gassend, G. E. Suh, D. Clarke, M. van Dijk and S. Devadas, "Caches and hash trees for efficient memory integrity verification," High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on, 2003, pp. 295-306.

[10] B. Rogers, S. Chhabra, M. Prvulovic and Y. Solihin, "Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly," Microarchitecture, 2007. MICRO 2007. 40th Annual IEEE/ACM International Symposium on, Chicago, IL, 2007, pp. 183-196.