Nayana Prasad Nagendra will present her general exam on Friday, May 13, 2016 at 10am in CS 402 The members of her committee are David August (adviser), David Wentzlaff, and Aarti Gupta. Everyone is invited to attend her talk, and those faculty wishing to remain for the oral exam following are welcome to do so. Her abstract and reading list follow below. For a full calendar view of all of the upcoming general exams, FPO's and Pre-FPO's, please go to the following link . HW-DSWP Abstract: Automatic parallelization by compiler is one way to better utilize multiple cores. Unfortunately, the best performing compiler techniques, such as those in the DSWP (Decoupled Software Pipelining) family of transformations, employ speculation and rely on dynamic information obtained by profiling, a technique unpopular with developers. Runtime techniques, such as Just-In-Time compilers, can address the popularity-of-profiling problem, but they are limited in the amount of dynamic information they can collect without negatively impacting overall program performance. Noting that existing processors already include structures that gather the type of information speculative thread extraction techniques need, I explore the possibility of performing thread extraction transformations in hardware and propose HW-DSWP (Hardware - DSWP) parallelization technique. The framework identifies hot loops based on the trace of backward branches, calculates dependency depth of instructions and segregates the instruction stream into critical and non-critical set which would then be executed on the main thread and additional thread respectively. Books: [1] John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach (5th Edition), 2011. [2] Andrew W. Appel, Modern Compiler Implementation in ML. Cambridge University Press, 1998 Reading List: [1] G. Ottoni, R. Rangan, A. Stoler, and D. August. “Automatic Thread Extraction with Decoupled Software Pipelining”. In 38th International Symposium on Microarchitecture (MICRO), November 2005 [2] E. Raman, G. Ottoni, A. Raman, M. J. Bridges, and D. August. “Parallel-Stage Decoupled Software Pipelining”. In the International Symposium on Code Generation and Optimization (CGO), April 2008 [3] R. Rangan, N. Vachharajani, M. Vachharajani, and D. I. August. “Decoupled Software Pipelining with the Synchronization Array”. In 13th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2004 [4] A. Cristal, O. Santana, F. Cazorla, M. Galluzzi, T. Ramirez, M. Pericas, and M.Valero. “Kilo-Instruction Processors: Overcoming the Memory Wall”. IEEE Micro, 25(3), May 2005. [5] S. Srinath, B. Ilbeyi, M. Tan, G. Liu, Z. Zhang, and C. Batten, “Architectural Specialization for Inter-Iteration Loop Dependence Patterns”. In the International Symposium on Microarchitecture (MICRO), December 2014 [6] S. Campanoni, K. Brownell, S. Kanev, T. M. Jones, G.-Y. Wei, and D. Brooks, “HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs”. In 41st International Symposium on Computer Architecture (ISCA), June 2014. [7] V. Govindaraju, C. H. Ho, and K. Sankaralingam. “Dynamically Specialized Datapaths for Energy Efficient Computing”. In 17th International Symposium on High-Performance Computer Architecture (HPCA), 2011 [8] S. Campanoni, T. M. Jones, G. Holloway, V. J. Reddi, G. Wei, and D. Brooks. "HELIX: Automatic Parallelization of Irregular Programs for Chip Multiprocessing". In CGO, 2012. [9] J. Yang, K. Skadron, M. Soffa, and K. Whitehouse. “Feasibility of Dynamic Binary Parallelization”. In 4th USENIX conference on Hot Topics in Parallelism, 2011 [10] F. Liu, H. Ahn, S. Beard, T. Oh, and D. August, “DynaSpAM: Dynamic Spatial Architecture Mapping Using out of Order Instruction Schedules”. In 42nd International Symposium on Computer Architecture (ISCA), 2015