EE Seminar Announcement - David Patterson, UC-Berkeley - November 11, 2015
Hi Res PRI_E_electrical_below_w-shield.jpg “Instruction Sets Want to Be Free: A Case for RISC-V” David Patterson, Professor, Electrical Engineering & Computer Science, University of California-Berkeley Wednesday, November 11, 2015 4:30 – 5:45 pm Reception to Follow Friend Center, Convocation Room Abstract: We start by quickly reviewing 50 years of computer architecture to show there is now widespread agreement on instruction set architecture (ISA). Unlike most other fields, despite this harmony there is no open alternative to proprietary offerings from ARM and Intel. Thus, we propose RISC-V (“RISC Five”), which targets Systems on a Chip (SoC). It has: * A small base of <50 classic RISC instructions that run a full open-source software stack. * Opcodes reserved for tailoring an SoC to applications. * Standard instruction extensions optionally included in an SoC. * Incorporated, as an open ISA, community suggestions before extensions are finalized. * A foundation to evolve the RISC-V slowly based solely on technical reasons voted on by members vs. by companies that inflate ISAs rapidly for business as well as technical reasons; ARM and Intel average about 2 new instructions per month. * No restrictions: there is no cost, no paperwork, and anyone can use it. Attendees will get a 2-page reference card (“green card”), which lists all RISC-V extensions, to contrast this minimal ISA with the 3,600-page x86 manual and the 5,400-page ARMv8 manual. We conclude by recapping 10 RISC-V chips built using Agile methods in just 4 years, including how shockingly cheap it is today to manufacture 100 2x2-mm, 28-nm chips. We used Chisel, a new hardware design language that reduces design effort by greatly increasing reuse. Bio: David Patterson joined UC Berkeley nearly 40 years ago. He has been Director of several research labs, Chair of Berkeley’s CS Division, Chair of the Computing Research Association, and President of ACM. His most successful projects are likely Reduced Instruction Set Computers (RISC), Redundant Arrays of Inexpensive Disks (RAID), and Network of Workstations (NOW), all of which helped lead to multi-billion-dollar industries. This research led to many papers, 6 books, and about 35 honors for him and his friends, including election to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He shared the IEEE von Neumann Medal and the NEC C&C Prize with John Hennessy, co-author of two of his books and President of Stanford University. Host: Ruby Lee, Forrest G. Hamrick Professor in Engineering, Professor of Electrical Engineering, Department of Electrical Engineering This seminar is supported with funds from the Korhammer Lecture Series
Hi Res PRI_E_electrical_below_w-shield.jpg “Instruction Sets Want to Be Free: A Case for RISC-V” David Patterson, Professor, Electrical Engineering & Computer Science, University of California-Berkeley Wednesday, November 11, 2015 4:30 – 5:45 pm Reception to Follow Friend Center, Convocation Room Abstract: We start by quickly reviewing 50 years of computer architecture to show there is now widespread agreement on instruction set architecture (ISA). Unlike most other fields, despite this harmony there is no open alternative to proprietary offerings from ARM and Intel. Thus, we propose RISC-V (“RISC Five”), which targets Systems on a Chip (SoC). It has: * A small base of <50 classic RISC instructions that run a full open-source software stack. * Opcodes reserved for tailoring an SoC to applications. * Standard instruction extensions optionally included in an SoC. * Incorporated, as an open ISA, community suggestions before extensions are finalized. * A foundation to evolve the RISC-V slowly based solely on technical reasons voted on by members vs. by companies that inflate ISAs rapidly for business as well as technical reasons; ARM and Intel average about 2 new instructions per month. * No restrictions: there is no cost, no paperwork, and anyone can use it. Attendees will get a 2-page reference card (“green card”), which lists all RISC-V extensions, to contrast this minimal ISA with the 3,600-page x86 manual and the 5,400-page ARMv8 manual. We conclude by recapping 10 RISC-V chips built using Agile methods in just 4 years, including how shockingly cheap it is today to manufacture 100 2x2-mm, 28-nm chips. We used Chisel, a new hardware design language that reduces design effort by greatly increasing reuse. Bio: David Patterson joined UC Berkeley nearly 40 years ago. He has been Director of several research labs, Chair of Berkeley’s CS Division, Chair of the Computing Research Association, and President of ACM. His most successful projects are likely Reduced Instruction Set Computers (RISC), Redundant Arrays of Inexpensive Disks (RAID), and Network of Workstations (NOW), all of which helped lead to multi-billion-dollar industries. This research led to many papers, 6 books, and about 35 honors for him and his friends, including election to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He shared the IEEE von Neumann Medal and the NEC C&C Prize with John Hennessy, co-author of two of his books and President of Stanford University. Host: Ruby Lee, Forrest G. Hamrick Professor in Engineering, Professor of Electrical Engineering, Department of Electrical Engineering This seminar is supported with funds from the Korhammer Lecture Series
participants (1)
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Nicole E. Wagenblast