Seminar speaker tomorrow: Prof. Josep Torrellas, UIUC
Hello all-- A final reminder: Prof. Josep Torrellas from UIUC will be visiting Princeton and giving a seminar on Tuesday April 30. The seminar will be from 12:30-1:30 in CS Room 302, with pizza beforehand starting at noon. Title/abstract below. I have reserved a 1-hour slot for him to meet with grad students from 2:30-3:30pm that day. That will occur in CS room 401. Any interested grad students can feel free to just show up for that. Thanks, Margaret ----------------------------------------------------------------- Toward Programmable High-Performance Multicores Josep Torrellas University of Illinois, Urbana-Champaign http://iacoma.cs.uiuc.edu/~torrellas One of the biggest challenges facing us today is how to design parallel architectures that attain high performance while efficiently supporting a programmable environment. In this talk, I describe novel organizations that will make the next generation of multicores more programmable and higher performance. Specifically, I show how to automatically reuse the upcoming transactional memory hardware for optimized code generation. Next, I describe a prototype of Record&Replay hardware that brings program monitoring for debugging and security to the next level of capability. I also describe a new design of hardware fences that is overhead-free and requires no software support. Finally, if time permits, I will outline architectural support to detect sequential consistency violations transparently. BIO: Josep Torrellas is a Professor of Computer Science and Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign (UIUC). He is a Fellow of IEEE and ACM. He is the Director of the Center for Programmable Extreme-Scale Computing, a center funded by DARPA, DOE, and NSF that focuses on architectures for extreme energy and power efficiency. He also directs the Intel-Illinois Parallelism Center (I2PC), a center created by Intel to advance parallel computing in clients. He has made contributions to parallel computer architecture in the areas of shared-memory multiprocessor organizations, cache hierarchies and coherence protocols, thread-level speculation, and hardware and software reliability. He received a Ph.D. from Stanford University. ------------------------------------------------------------ Margaret Martonosi Hugh Trumbull Adams '35 Professor of Computer Science Princeton University http://www.princeton.edu/~mrm mrm@princeton.edu
Margaret, My sister has changed her appointment to late afternoon. I can still meet with Josep at 1:30pm. Kai ----- Original Message ----- | Hello all-- | A final reminder: | Prof. Josep Torrellas from UIUC will be visiting Princeton and giving | a seminar on Tuesday April 30. The seminar will be from 12:30-1:30 | in CS Room 302, with pizza beforehand starting at noon. | Title/abstract below. | I have reserved a 1-hour slot for him to meet with grad students from | 2:30-3:30pm that day. That will occur in CS room 401. Any interested | grad students can feel free to just show up for that. | Thanks, | Margaret | ----------------------------------------------------------------- | Toward Programmable High-Performance Multicores | Josep Torrellas | University of Illinois, Urbana-Champaign | http://iacoma.cs.uiuc.edu/~torrellas | One of the biggest challenges facing us today is how to design | parallel | architectures that attain high performance while efficiently | supporting | a programmable environment. In this talk, I describe novel | organizations | that will make the next generation of multicores more programmable | and | higher performance. Specifically, I show how to automatically reuse | the | upcoming transactional memory hardware for optimized code generation. | Next, | I describe a prototype of Record&Replay hardware that brings program | monitoring for debugging and security to the next level of | capability. I | also describe a new design of hardware fences that is overhead-free | and | requires no software support. Finally, if time permits, I will | outline | architectural support to detect sequential consistency violations | transparently. | BIO: | Josep Torrellas is a Professor of Computer Science and | Electrical and Computer Engineering at the University of Illinois at | Urbana-Champaign (UIUC). He is a Fellow of IEEE and ACM. He is the | Director of the Center for Programmable Extreme-Scale Computing, a | center funded by DARPA, DOE, and NSF that focuses on architectures | for | extreme energy and power efficiency. He also directs the | Intel-Illinois | Parallelism Center (I2PC), a center created by Intel to advance | parallel | computing in clients. He has made contributions to parallel computer | architecture in the areas of shared-memory multiprocessor | organizations, | cache hierarchies and coherence protocols, thread-level speculation, | and hardware and software reliability. He received a Ph.D. from | Stanford University. | ------------------------------------------------------------ | Margaret Martonosi | Hugh Trumbull Adams '35 Professor of Computer Science | Princeton University | http://www.princeton.edu/~mrm | mrm@princeton.edu | _______________________________________________ | talks mailing list | talks@lists.cs.princeton.edu | https://lists.cs.princeton.edu/mailman/listinfo/talks
participants (2)
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Kai Li -
Margaret Martonosi