Sent on behalf of Prof. Kaushik Sengupta **Refreshments at 1 pm and a chance to talk with speakers ** cid:image002.png@01D12619.798B8680IEEE SSCS Lehigh/Princeton/Columbia Chapters Present cid:image004.jpg@01D12619.798B8680 Distinguished Lecture Colloquia, December 2015 cid:image005.png@01D12619.798B8680 Speaker: Prof . Jan Van der Spiegel University of Pennsylvania Talk Title : Bio-inspired Polarization Imagers - Making the invisible visible Date: Thursday, December 3, 2015 Time: 1:30 – 2:45 p.m. Location: Princeton University, Department of Electrical Engineering Engineering Quadrangle, Room B205 Olden Street Princeton, NJ 08544 Abstract: Biology provides us with fascinating examples of intelligent, low power, and highly efficient sensory systems. With the advances in CMOS technology, it has become feasible to build microelectronic systems that mimic some of the key features found in biology. This talk will focus on CMOS vision sensors for polarization imaging. We will review briefly the concepts of polarization and how it is used by various species in nature to enhance their vision or to aid with navigation and communication. Inspired by the biology we have explored polarization for a variety of applications to detect features that are hard to see or even invisible to the human eye. More recent results from the literature including the use of polarization imaging for disease detection will be reviewed. Motivated by the potential advantages of polarization imaging, we have developed a CMOS imager that combines the pixel array with micropolarizers and on-chip processing. Details of the design and polarizer optimization will be described. Speaker: Prof . Francesco Svelto, Università di Pavia, Italy Talk Title : On the design of circuits for frequency synthesizers at MM-waves in foto Frankultra scaled CMOS Date: Thursday, December 3, 2015 Time: 3:00 – 4:15 p.m. Location: Princeton University, Department of Electrical Engineering Engineering Quadrangle, Room B205 Olden Street Princeton, NJ 08544 Abstract: Transceivers for wireless communications at millimeter-waves are becoming pervasive in several commercial fields. Taking advantage of a cut-off frequency of hundreds of GHz, CMOS technology is rapidly expanding from Radio Frequency to Millimeter-Waves, thus enabling low-cost compact solutions. The question we raise in this talk is whether scaling is just providing advantages at mm-waves or not. We present experimental data of single devices, comparing 65nm and 32nm nodes in a wide-frequency range. In particular, switches used in VCOs for tank components tuning, MOM and AMOS capacitors, inductors. f T and f MAX increase though slower than in the past, r on *C off , a figure of merit for switches, improves correspondingly. As a consequence, wide-band circuits benefit from scaling to 32nm. As an example, a frequency divider-by-4, based on differential pairs used as dynamic latches, realized in both technology nodes and able to operate up to 108GHz, is discussed. On the contrary, passive components do not improve and eventually degrade their performances. As a consequence, a conventional LC VCO, relying on tank quality factor, is not expected to improve. In this work we discuss a new topology for Voltage Controlled Oscillators, based on inductor splitting, showing low noise and wide tuning range in ultra-scaled nodes. Speaker: Prof. Borivoje Nikolić University of California, Berkeley Talk Title : Resilient, Wide-Voltage-Range RISC-V Processors in 28nm Technologies Borivoje_Nikolic (1)Date: Thursday, December 3, 2015 Time: 4:30 – 5:45 p.m. Location: Princeton University, Department of Electrical Engineering Engineering Quadrangle, Room B205 Olden Street Princeton, NJ 08544 Abstract: This talk presents a design of an energy-efficient microprocessor that implements several techniques for operation in a very wide voltage range. A particular implementation is based on an open Berkeley RISC-V architecture. To enable agile dynamic voltage and frequency scaling, with high energy efficiency the design implements an integrated switched-capacitor DC-DC converter. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read. Architectural resiliency techniques include the use of error correction and dynamic column redundancy. The processor is implemented by using an agile design methodology. Contact Info: Nagi Naganathan, nagisub@gmail.com or Kaushik Sengupta, kaushiks@princeton.edu