21440 transmit problems

[Tammo Spalink]

I am currently unable to transmit data using the 21440 on the IXP1200
evaluation board.  I hope someone can give me some insight into what I
may be doing wrong.  I am only having problems with transmit, my
receive code appears to work fine.  I have two of the 100Mbps ports
connected by a Xover cable.  All I am trying to do is send a minimal
ethernet packet from one port to the other.

Here is a minimal program that exhibits my problem (I load it into the
S-ARM with the VxWorks loader).  I am presenting pseudo-code for
readability.  I can send you real code too if that helps.


// Initialize 21440 ports 6 & 7 which are connected by an X-cable

// The port CSRs are at offsets 0x38406000 and 0x38407000 respectively.
// PORT_CTR is at 0x14, FFO_BUS at 0x48, TX_ERR_MOD at 0x50, and
// TX_TSHD_BOFF at 0x54 from the initial offsets.

PORT_CTR     = PTRST & CTRST
PORT_CTR     = CNRST
FFO_BUS      = BEND
TX_ERR_MOD   = XCLS & LCLS & UNFS
TX_TSHD_BOFF = 0xAF (BLK = 84 bytes, TSD = 124 bytes)
PORT_CTR     = TXEN & RXEN
INT_EN       = STOPE & OVFCE & LNCHE & TXERE & TXOKE & RXEVE & RXOKE


// Initialize the IX bus

RDYBUS_TEMPLATE_PROG       = 0xFFFFFFF7, 0xFFFFFFFB, 0xFFFFFFFF
RDYBUS_SYNCH_COUNT_DEFAULT = 0
RCV_RDY_CTL                = 0
XMIT_RDY_CTL               = 0
RDYBUS_TEMPLATE_CTL        = ER & TM & MS


// Initialize a packet in SRAM

static uint8 packet[] = {
    0x11, 0x12, 0x13, 0x14, 0x15, 0x16,
    0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
    0x00, 0x06,
    0x01, 0x02, 0x03, 0x04, 0x05, 0x06
};

I copy this into SRAM and print it out again to verify that the copy
worked correctly.  BTW, is SRAM little-endian?

// Initialize and start a uEngine

I use it to run the following uCode program.

---- Start uCode -----
#macro imm32 [destReg, const]
        immed_w1 [destReg, ((const >> 16) & 0xFFFF)]
        immed_w0 [destReg,  (const        & 0xFFFF)]
#endm

#macro imm16 [destReg, const]
        immed [destReg, const]
#endm

#macro move [destReg, srcReg]
        alu [destReg, --, B, srcReg]
#endm
   
#macro set_field [reg, offset, val]
        alu [reg, reg, OR, val, offset]
#endm

#define BUFFER   0x1400          ; SRAM packet buffer

.xfer_order $xfer0 $xfer1 $xfer2 $xfer3 $xfer4 $xfer5 $xfer6 $xfer7

        imm32   [sram_addr, BUFFER]
        imm16   [tfifo_addr, 0]

        sram      [read, $xfer0, sram_addr, 0, 8], ctx_swap
        t_fifo_wr [$xfer0, tfifo_addr, 0, 4], ctx_swap
        
        imm16     [control, 0]
        set_field [control, <<0,  6] ; PID
        set_field [control, <<7,  0] ; ERR
        set_field [control, <<8,  1] ; SOP
        set_field [control, <<9,  1] ; EOP
        set_field [control, <<10, 3] ; VLD
        set_field [control, <<13, 2] ; QWD
        set_field [control, <<16, 0] ; PREP
        set_field [control, <<17, 0] ; TXASIS
        set_field [control, <<18, 0] ; TXER
        move      [$xfer0, control]
        imm16     [$xfer1, 0]
        
        imm16     [tfifo_addr, 128]
        t_fifo_wr [$xfer0, tfifo_addr, 0, 1], ctx_swap

        fast_wr   [0, xmit_validate]

        fast_wr [1, thread_done]
        ctx_arb [kill]
---- End uCode -----

CONCLUSION:

I expected that after this code ran (after the thread_done signal), I
would get an TXOK interrupt on port 6 and an RXOK interrupt on port 7.
However, all that happens is that XMIT_PTR is incremented from 0 to 1
and nothing else.  What am I missing/forgetting?

Thanks for any help or suggestions,

Tammo