Loading MicroEngine code

[Paige, Dale W]

The vxWorks BSP does enable the MMU, and caching for a certain region in
SDRAM.  It sets this up correctly (see
<ixp1200>\boardsupport\vxWorks\ixp1200eb\rominit.s).   I do not think you
need to, or should, disable the MMU to solve this problem.

-----Original Message-----
From: Tammo Spalink [mailto:tspalink at CS.Princeton.EDU]
Sent: Friday, June 09, 2000 8:39 AM
To: ixp1200 at CS.Princeton.EDU
Subject: Re: Loading MicroEngine code 



I am using the vxWorks boot loader to load my test program directly to
the SACore (no OS).  Does the boot loader enable the MMU and data
cache (which I believe are disabled at reset)?

I am working on adding the code to disable these (MMU & caches).

However, the behavior I get is that I write to the CSR memory region
and am unable to read back what I wrote.  If I understand the side
effects of caching/buffering correctly, I should definately be able to
read what it wrote, but the write may not have propagated to the
device correctly.  No?

Tammo

On Thu,  8 Jun 2000, "Paige, Dale W" wrote:
> What OS are you running?
> 
> Are you certain that the SA core is treating data accesses to the CSR
range
> data as non-cacheable and non-bufferable?
> 
> -----Original Message-----
> From: Tammo Spalink [mailto:tspalink at CS.Princeton.EDU]
> Sent: Thursday, June 08, 2000 2:09 PM
> To: ixp1200 at CS.Princeton.EDU
> Subject: Re: Loading MicroEngine code 
> 
> 
> 
> No effect I am afraid.
> 
> Tammo
> 
> On Thu,  8 Jun 2000, "Paige, Dale W" wrote:
> > Tammo - 
> > 
> > Try writting the address again prior to the read.
> > 
> >     csrWrite(CSR, USTORE_ADDR, addr);       // Set the target address
> >     csrWrite(CSR, USTORE_DATA, 0xD8100020); // Write an instruction
> >     csrWrite(CSR, USTORE_ADDR, addr);       // Set the target address
> AGAIN
> > <==
> >     result = csrRead(CSR, USTORE_DATA);