[ixp1200] question on behavior of IXF440/IXF1002

[Johnson, Erik J]

It isn't correct for the software to send two receive requests as you have
described in this scenario.  When the MAC asserts the receive ready bit for
a port it means (unless configured differently) that 1 mpacket is available.
Before issuing the second receive request the software must wait for the
receive ready bit to both get updated (i.e., the ready bus sequencer must
poll the MAC and update the receive ready CSR) and be set.  You will get
unpredictable results when doing this on the IXF440.

Of course, this is only true of the IXF440, not the IXF1002, since the
IXF1002 can be sent speculative receive requests.  In your scenario, the
IXF1002 will send a cancelled receive control message for the second
request.


erik

> -----Original Message-----
> From: Wen Xu [mailto:wxu at CS.Princeton.EDU]
> Sent: Wednesday, April 17, 2002 7:57 AM
> To: ixp1200 at CS.Princeton.EDU
> Subject: [ixp1200] question on behavior of IXF440/IXF1002
> 
> 
> Hi,
> 
> My question is like this:
> 
> In the middle of receiving a 1500 byte packet, if at some 
> point the MAC 
> has 100 bytes in its Receive FIFO (but the end of packet is not there 
> yet) and set the ready flag, but two data requests come to the port 
> instead of one.
> 
> Will the MAC send 36 bytes of data for the second request? Or will it
> simply assert error for the second request, keeping the 36 byte in the
> Receive FIFO for next data request?
> 
> Wen
>