- talks - lists.cs.princeton.edu

Colloquium Speaker Trevor Darrell Thurs Oct 16, 4:30pm
by Nicole E. Wagenblast 10 Oct '14

10 Oct '14

Large-Scale Detector Adaptation and Other Recent Results Trevor Darrell , University of California, Berkeley Thursday, October 16, 4:30pm Computer Science 105 In this talk I'll review recent progress towards robust and effective perceptual representation learning. I'll describe new methods for large-scale detection, whereby robust detectors can be learned from weakly labeled training data, following paradigms of domain adaptation and multiple instance learning. I'll discuss how such models can be used not only for detection but also for pose prediction and further for effective fine-grained recognition, extending traditional convolutional neural network models to include explicit pose-normalized descriptors. Finally, and time permitting (pardon the pun), I'll review our recent work on anytime recognition, which provides methods that strive to provide the best answer possible, even with a limited (and unknown) time budget. Prof. Trevor Darrell’s group is co-located at the University of California, Berkeley, and the UCB-affiliated International Computer Science Institute (ICSI), also located in Berkeley, CA. Prof. Darrell is on the faculty of the CS Division of the EECS Department at UCB and is the vision group lead at ICSI. Darrell’s group develops algorithms for large-scale perceptual learning, including object and activity recognition and detection, for a variety of applications including multimodal interaction with robots and mobile devices. His interests include computer vision, machine learning, computer graphics, and perception-based human computer interfaces. Prof. Darrell was previously on the faculty of the MIT EECS department from 1999-2008, where he directed the Vision Interface Group. He was a member of the research staff at Interval Research Corporation from 1996-1999, and received the S.M., and PhD. degrees from MIT in 1992 and 1996, respectively. He obtained the B.S.E. degree from the University of Pennsylvania in 1988, having started his career in computer vision as an undergraduate researcher in Ruzena Bajcsy's GRASP lab.

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Colloquium Speaker: Rahul Sukthankar, Thurs. Oct. 9 4:30pm
by Nicole E. Wagenblast 09 Oct '14

09 Oct '14

The CouchPotato Project: Learning Visual Concepts by Watching YouTube Rahul Sukthankar ( Google Research ) Thursday, October 9, 4:30pm Computer Science 105 What could computers learn about visual concepts, such as objects and actions, by watching large quantities of internet video, with minimal human supervision? In this talk, I will present several of our recent explorations in this area, including spatio-temporal object segmentation in video, weakly-supervised learning of human actions and unsupervised discovery of motion patterns in animal videos. The talk includes research contributions from many colleagues at Google, interns and faculty colleagues: L. Del Pero, I. Essa, L. Fei-Fei, V. Ferrari, M. Grundmann, G. Hartmann, J. Hoffman, A. Karpathy, T. Leung, V. Kwatra, O. Madani, J. Rehg, S. Ricco, S. Shetty, K. Tang, G. Toderici, D. Tsai, J. Yagnik. Rahul Sukthankar is a scientist at Google Research, an adjunct research professor in the Robotics Institute at Carnegie Mellon and courtesy faculty at UCF. He was previously a senior principal researcher at Intel Labs, a senior researcher at HP/Compaq and research scientist at Just Research. Rahul received his Ph.D. in Robotics from Carnegie Mellon in 1997 and his B.S.E. in Computer Science from Princeton in 1991. His current research focuses on computer vision and machine learning, particularly in the areas of object recognition and video understanding.

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Andrej Risteski will present his Generals on Tuesday, Oct. 14th at 10:30am in CS 302
by Nicki Gotsis 07 Oct '14

07 Oct '14

Andrej Risteski will present his Generals on Oct. 14th at 10:30am in CS 302 The members of his committee are Sanjeev Arora, Moses Charikar, and David Blei. Everyone is invited to attend the talk, and those faculty wishing to remain for the oral exam following are welcome to do so. His abstract and reading list follow below. Abstract: Variational methods are a fairly commonly used tool in machine learning to solve inference problems of various kinds. The way they work is to reduce the problem of calculating some posterior probability to a suitable, usually non-convex, mathematical program. This is then solved using some form of alternating minimization. The vanilla form of this is expectation maximization (EM), and some more sophisticated flavors are variational Bayes, expectation propagation, etc. Unfortunately, all of these rarely come with any guarantees, and even in practice are prone to local optima. I will discuss some simple cases where these methods, along with suitable initialization, converge to the right value, mostly in the setting of topic models. Reading list: 0. Algorithm Design; Kleinberg, Tardos 1. Graphical Models, Exponential Families, and Variational Inference; Jordan, Wainwright [Chapters 1,2,3,4,7,9] 2. Latent Dirichlet Allocation; Blei, Ng, Jordan 3. Learning Topic Models - Going beyond SVD; Arora, Ge, Moitra 4. A Practical Algorithm for Topic Modeling with Provable Guarantees; Arora et al. 5. Computing a Nonnegative Matrix Factorization --- Provably; Arora, Ge, Kannan, Moitra 6. Complexity of Inference in Graphical Models; Chandresekaran, Srebro, Harsha 7. Understanding Belief Propagation and its Generalizations; Yedidia, Freeman, Weiss 8. Convexity Arguments for Efficient Minimization of the Bethe and Kikuchi Free Energies; Heskes 9. Convexifying the Bethe Free Energy; Meshi, Jaimovich, Globerson, Friedman 10. Counting independent sets up to the tree threshold; Weitz 11. Counting Independent Sets Using the Bethe Approximation; Chandrasekaran, Chertkov, Gamarnik, Shah, Shin 12. Clustering with Spectral Norm and the k-means Algorithm; Kumar, Kannan

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4:30pm Tue Oct 7 talk on multipath routing in CS 402
by Jennifer Rexford 06 Oct '14

06 Oct '14

Speaker: Deep Medhi, University of Missouri-Kansas City Title: Is Multipath Routing Beneficial? Date/time: 4:30pm Tuesday October 7 Location: CS 402 Abstract: It's often believed that multipath routing is always beneficial. Taking a traffic engineering perspective, we consider commonly used goals such as congestion minimization, minimum average delay, and minimum cost routing. Using a well-known result from linear programming, we show that numbers of paths taken by all demands at optimality is limited by the total number of demands and links in a network. When all node pairs (demands) in a network have traffic, multipath routing essentially becomes single-path routing, especially as the network becomes large. Under certain traffic conditions, single-path routing is found to be optimal. We will also present results on a number of traffic scenarios and load conditions using topologies used by ISPs and in data center networks. These observations are counter-intuitive due to our commonly held belief about multipath routing. Bio: Deep Medhi is Curators' Professor in the Department of Computer Science and Electrical Engineering at the University of Missouri-Kansas City, USA. He received B.Sc. in Mathematics from Cotton College, Gauhati University, India, M.Sc. in Mathematics from the University of Delhi, India, and his Ph.D. in Computer Sciences from the University of Wisconsin-Madison, USA. Prior to joining UMKC in 1989, he was a member of the technical staff at AT&T Bell Laboratories. He was an invited visiting professor at the Technical University of Denmark, a visiting research fellow at Lund Institute of Technology, Sweden, a research visitor at University of Campinas, Brazil under the Brazilian Science Mobility Program and served as a Fulbright Senior Specialist. He is the Editor-in-Chief of Springer’s Journal of Network and Systems Management, and is on the editorial board of IEEE/ACM Transactions on Networking, IEEE Transactions on Network and Service Management, and IEEE Communications Surveys & Tutorials. He is co-author of the books, Routing, Flow, and Capacity Design in Communication and Computer Networks (2004) and Network Routing: Algorithms, Protocols, and Architectures (2007), both published by Morgan Kauffman/Elsevier.

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Fwd: EE Seminar - October 7, 2014, 12:00 pm, E-Quad B327 - Dr. Wei Wang
by Jennifer Rexford 06 Oct '14

06 Oct '14

> > Speaker: Dr. Wei Wang > Beijing Jiaotong University > Title: Automated Detection and Analysis of Malicious Android Apps > Date: Tuesday, October 7, 2014 > Time: 12:00 p.m. > Room: E-Quad, Room B327 > Host: Prof. Ruby Lee > > > Abstract: Android has been a major target of malicious applications (malapps). How to automate the detection and analysis of malapps is an important issue. We will present three parts of our recent work. First, we explore the permission-induced risk in Android apps in a systematic manner. Second, we extract as many as possible static features from Android apps for the detection and analysis of malapps. Third, we extract structural features from apps for the analysis. The preliminary results show the automated process of the detection and analysis of malicious apps. > > Biography: Dr. Wei Wang is currently associate professor in the Department of Information SecuriBeijing Jiaotong University, China. He earned his Ph.D. degree from Xi’an Jiaotong University, in 2006. He was a postdoctoral researcher in University of Trento, Italy, during 2005-2006. He was a postdoctoral researcher in TELECOM Bretagne and in INRIA, France, during 2007-2008. He was a European ERCIM Fellow in Norwegian University of Science and Technology (NTNU), Norway, and in Interdisciplinary Centre for Security, Reliability and Trust (SnT), University of Luxembourg, during 2009-2011. He visited INRIA, ETH, NTNU, CNR, and New York University Polytechnic. He has authored or co-authored over 40 peer-reviewed papers in various journals and international conferences. His main research interests include mobile, computer and network security. >

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Update: Wenhao Jia (ELE) presents FPO "Analysis and Optimization Techniques for Massively Parallel Processors" Tuesday, October 7 at 9am, Equad Room J401
by Nicki Gotsis 01 Oct '14

01 Oct '14

Wenhao Jia FPO Date and Location: Tuesday, October 7 at 9am, Equad Room J401 Thesis Committee: Co-advisors: Margaret Martonosi and Kelly Shaw; Reader: Niraj Jha; Non-readers: David August and Sharad Malik Thesis Title: Analysis and Optimization Techniques for Massively Parallel Processors Thesis Abstract: Heterogeneous parallelism has emerged as a widespread computing paradigm in the past decade or so. In particular, massively parallel processors such as graphics processing units (GPUs) have become the prevalent throughput computing element in heterogeneous systems. However, GPUs are difficult to program and design, primarily due to developers' general unfamiliarity with GPUs, a lack of hardware resource virtualization, and inadequate tailoring of conventionally designed components--such as general-purpose caches--to the massively parallel nature of GPU workloads. To overcome these challenges, this thesis proposes statistical analysis techniques and software and hardware optimizations that improve the performance, power efficiency, and programmability of GPUs. These proposals make it easier for programmers and designers to produce optimized GPU software and hardware designs. The first part of the thesis describes how statistical analysis can help users explore a GPU software or hardware design space with performance or power as the metric of interest. In particular, two fully automated tools--linear regression-based Stargazer and regression tree-based Starchart--are developed and presented. They help identify important design parameters and automate design decisions, while saving design exploration time by 300-3000 times compared to exhaustive approaches. Then, the second part of the thesis proposes two compile-time algorithms to automatically make two key GPU software design decisions: cache configuration and thread block size selection. The first algorithm uses instruction-level memory access pattern analysis and cache control to improve the performance benefits of caching from 5.8% to 18%. The second algorithm runs programs with thread counts estimated to trigger performance saturation, reducing GPU core resource usage by 27-62% while improvin g performance by 5-10%. Finally, the third part of the thesis proposes and evaluates the memory request prioritization buffer (MRPB). MRPB uses request reordering to reduce cache thrashing and uses cache bypassing to reduce resource stalls, improving performance by 1.3-2.7 times and easing GPU programming. In summary, using GPUs as an example, the high-level statistical tools and the more focused software and hardware studies presented in this thesis demonstrate how to use automation techniques to effectively improve the performance, power efficiency, and programmability of emerging heterogeneous computing platforms. _______________________________________________ talks mailing list talks(a)lists.cs.princeton.edu To edit subscription settings or remove yourself, use this link: https://lists.cs.princeton.edu/mailman/listinfo/talks

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Wenhao Jia (ELE) presents FPO "Analysis and Optimization Techniques for Massively Parallel Processors" Wednesday, October 8 at 3pm, Equad Room J401
by Nicki Gotsis 01 Oct '14

01 Oct '14

Wenhao Jia FPO Date and Location: Wednesday, October 8 at 3pm, Equad Room J401 Thesis Committee: Co-advisors: Margaret Martonosi and Kelly Shaw; Reader: Niraj Jha; Non-readers: David August and Sharad Malik Thesis Title: Analysis and Optimization Techniques for Massively Parallel Processors Thesis Abstract: Heterogeneous parallelism has emerged as a widespread computing paradigm in the past decade or so. In particular, massively parallel processors such as graphics processing units (GPUs) have become the prevalent throughput computing element in heterogeneous systems. However, GPUs are difficult to program and design, primarily due to developers' general unfamiliarity with GPUs, a lack of hardware resource virtualization, and inadequate tailoring of conventionally designed components--such as general-purpose caches--to the massively parallel nature of GPU workloads. To overcome these challenges, this thesis proposes statistical analysis techniques and software and hardware optimizations that improve the performance, power efficiency, and programmability of GPUs. These proposals make it easier for programmers and designers to produce optimized GPU software and hardware designs. The first part of the thesis describes how statistical analysis can help users explore a GPU software or hardware design space with performance or power as the metric of interest. In particular, two fully automated tools--linear regression-based Stargazer and regression tree-based Starchart--are developed and presented. They help identify important design parameters and automate design decisions, while saving design exploration time by 300-3000 times compared to exhaustive approaches. Then, the second part of the thesis proposes two compile-time algorithms to automatically make two key GPU software design decisions: cache configuration and thread block size selection. The first algorithm uses instruction-level memory access pattern analysis and cache control to improve the performance benefits of caching from 5.8% to 18%. The second algorithm runs programs with thread counts estimated to trigger performance saturation, reducing GPU core resource usage by 27-62% while improving performance by 5-10%. Finally, the third part of the thesis proposes and evaluates the memory request prioritization buffer (MRPB). MRPB uses request reordering to reduce cache thrashing and uses cache bypassing to reduce resource stalls, improving performance by 1.3-2.7 times and easing GPU programming. In summary, using GPUs as an example, the high-level statistical tools and the more focused software and hardware studies presented in this thesis demonstrate how to use automation techniques to effectively improve the performance, power efficiency, and programmability of emerging heterogeneous computing platforms.

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IEEE SSCS Distinguished Lecture Series at Princeton - October 16, 2014 - E-Quad B205
by Nicole E. Wagenblast 01 Oct '14

01 Oct '14

S ent on behalf of Prof. Kaushik Sengupta IEEE SSCS Lehigh/Princeton/Columbia Chapters Present Distinguished Lecture Colloquia, October 2014 October 16, 2014, 1:30–2:45 pm On-Chip Voltage and Timing Diagnostic Circuits Frank O’Mahony, Intel Abstract: This talk introduces a set of practical and powerful techniques and circuits to observe and characterize on-die circuitry. Measuring voltage and timing information on the chip itself alleviates the bandwidth and noise limitations associated with bringing signals off-chip to be measured. Specific applications of these techniques include measurement and characterization of power supply noise, power delivery impedance, clock skew, phase interpolator linearity, I/O eye margins, waveform capture, RX voltage noise and hysteresis, and RX clock-data jitter. Because the measurements are fully integrated, the rest of the system can be automatically adapted based on these metrics in a stand-alone manner. Best of all, many of these techniques leverage existing circuitry and are highly digital. October 16, 2014, 3:00–4:15 p.m. Millimeter-wave and Terahertz Integrated Circuits in Silicon Technologies: Challenges and Solutions Prof. Payam Hedari, University of California Irvine Abstract: The vastly under-utilized spectrum across millimeter-wave (mm-wave) and terahertz (THz) bands has generated great deal of excitement to investigate futuristic systems for 10+ gigabit short-range wireless as well as wideband sensing/imaging applications. Simply put, the shorter wavelength associated with the mm-wave/THz band is appealing since the physical dimensions of the antenna and associated electronics are reduced in size, making it possible to design multi-antenna structures to achieve beamforming, spatial diversity and multiplexing. Owing to aggressive scaling in feature size and device fT/fmax, nanoscale (Bi)CMOS technology potentially enables integration of sophisticated systems at THz frequency range, once only be implemented in compound III-IV semiconductor technologies. This talk will give an overview of recent advances in designing silicon-based integrated circuits will be capable of operating close to the maximum operation limits of silicon-based transistors. The talk then will discuss in depth about two case studies designed in UCI’s Nanoscale Communication Integrated Circuits (NCIC) Labs; namely, the world’s highest fundamental frequency fully differential transceiver in CMOS at 210 GHz, and the world’s highest frequency PLL-based Synthesizer in Silicon at 300GHz with a wide tuning range. October 16, 2014, 4:30–5:45 p.m. Low-Power, High-Bandwidth, and Ultra-Small Memory Module Design Prof. R. Jacob Baker, University of Nevada, Las Vegas Abstract: This work proposes a novel DRAM module and interconnect architectures in an attempt to improve computing energy use and performance. A low cost advanced packaging technology is used to propose an 8 die and 32-die memory module. The 32-die memory module measures less than 2 cm3. The size and packaging technique allow the memory module to consume less power than conventional module designs. A 4 Gb DRAM architecture utilizing 64 data pins is proposed. The DRAM architecture is inline with ITRS roadmaps and can consume 50% less power while increasing bandwidth by 100%. The large number of data pins are supported by a low power capacitive-coupled interconnect. The receivers developed for the capacitive interface were fabricated in 0.5 μm and 65 nm CMOS technologies. The 0.5 μm design operated at 200 Mbps, used a coupling capacitor of 100 fF, and consumed less than 3 pJ/bit of energy. The 65 nm design operated at 4 Gbps, used a coupling capacitor of 15 fF, and consumed less than 15 fJ/bit and order of magnitude smaller consumptions than previously reported receiver designs. Contact Info: Nagi Naganathan, nagisub(a)gmail.com or Kaushik Sengupta, kaushiks(a)princeton.edu

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Princeton Day of Statistics
by Nicole E. Wagenblast 29 Sep '14

29 Sep '14

Dear all, We are pleased to announce the 4th Princeton Day of Statistics. This bi-annual event will take place on Friday, October 17, 2014 in Sherrerd 101. Seven speakers will deliver talks on the most recent advances in statistics. * Marten Wegkamp (Cornell University) * Tony Cai (University of Pennsylvania) * Christopher Genovese (Carnegie Mellon University) * Jun Liu (Harvard University) * Regina Liu (Rutgers University) * Richard A. Davis (Columbia University) * Kung-Sik Chan (University of Iowa) For more information and registration, visit http://orfe.princeton.edu/statlab/events/pds Registration is required to attend, deadline is October 10th. Regards, Han Liu Assistant professor Operations Research & Financial Engineering Dept. -- Carol Smith Academic Assistant & Events Coordinator 609-258-9863 Fax: 609-258-4363 carols(a)princeton.edu

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4:30pm Tue Oct 7 talk on multipath routing in CS 402
by Jennifer Rexford 26 Sep '14

26 Sep '14

Speaker: Deep Medhi, University of Missouri-Kansas City Title: Is Multipath Routing Beneficial? Date/time: 4:30pm Tuesday October 7 Location: CS 402 Abstract: It's often believed that multipath routing is always beneficial. Taking a traffic engineering perspective, we consider commonly used goals such as congestion minimization, minimum average delay, and minimum cost routing. Using a well-known result from linear programming, we show that numbers of paths taken by all demands at optimality is limited by the total number of demands and links in a network. When all node pairs (demands) in a network have traffic, multipath routing essentially becomes single-path routing, especially as the network becomes large. Under certain traffic conditions, single-path routing is found to be optimal. We will also present results on a number of traffic scenarios and load conditions using topologies used by ISPs and in data center networks. These observations are counter-intuitive due to our commonly held belief about multipath routing. Bio: Deep Medhi is Curators' Professor in the Department of Computer Science and Electrical Engineering at the University of Missouri-Kansas City, USA. He received B.Sc. in Mathematics from Cotton College, Gauhati University, India, M.Sc. in Mathematics from the University of Delhi, India, and his Ph.D. in Computer Sciences from the University of Wisconsin-Madison, USA. Prior to joining UMKC in 1989, he was a member of the technical staff at AT&T Bell Laboratories. He was an invited visiting professor at the Technical University of Denmark, a visiting research fellow at Lund Institute of Technology, Sweden, a research visitor at University of Campinas, Brazil under the Brazilian Science Mobility Program and served as a Fulbright Senior Specialist. He is the Editor-in-Chief of Springer’s Journal of Network and Systems Management, and is on the editorial board of IEEE/ACM Transactions on Networking, IEEE Transactions on Network and Service Management, and IEEE Communications Surveys & Tutorials. He is co-author of the books, Routing, Flow, and Capacity Design in Communication and Computer Networks (2004) and Network Routing: Algorithms, Protocols, and Architectures (2007), both published by Morgan Kauffman/Elsevier.

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