- talks - lists.cs.princeton.edu

Diego Perez Botero MSE thesis talk
by Melissa M. Lawson 26 Apr '13

26 Apr '13

Diego Perez Botero will present his MSE thesis talk on Friday May 3 at 2PM in Room 301 (note room!). The members of his committee are: Ruby Lee (ELE), advisor and Jennifer Rexford, reader. Everyone is invited to attend his talk. His abstract follows below. ---------------------- TITLE Pwnetizer: Improving Availability in Cloud Computing through Fast Cloning and I/O Randomization ABSTRACT The rise of the Cloud Computing paradigm has led to security concerns amongst its adopters, given that resources are shared and mediated by a Hypervisor which may be targeted by rogue guest Virtual Machines (VMs) and remote attackers. We conducted a thorough analysis of the codebase of two popular open-source Hypervisors, Xen and KVM, followed by an extensive study of the vulnerability reports associated with them. Based on our findings, we propose a practical characterization of Hypervisor vulnerabilities. From this analysis, we see that more than one third of all attacks are due to device emulation and that availability breaches are by far the most common security breaches, considering the cornerstone security properties of Confidentiality, Integrity and Availability. We developed Pwnetizer, a novel VM cloning strategy, to address these weaknesses of virtualized environments. Pwnetizer facilitates increased availability by rapidly generating clone VMs that can instantly contribute to the overall throughput of a Cloud Customer's applications, as they increase the resources available to it (network bandwidth, CPU and RAM). Previously, VM Cloning research has prioritized the performance of computationally-intensive workloads by enabling the creation of transient clone VMs that depend on a master VM. Meanwhile, the few alternatives able to generate fully-independent stateful VM Clones suffer from considerable downtimes (tens of seconds), which is itself a loss of availability. A KVM-based prototype of our Pwnetizer solution is able to gracefully generate on-demand independent VM Clones with sub-second downtimes. At minimal additional overhead, our cloning technology also randomizes the device drivers employed by each clone VM. This takes advantage of the variety of device drivers with overlapping functionality supported by commodity Hypervisors. Without having to vet them beforehand, we defend a set of diversified clone VMs against current and future attacks on device drivers with security vulnerabilities. This further improves availability by preventing large-scale VM crashes caused by attacks made possible by device emulation bugs.

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Dushyant Arora MSE thesis talk
by Melissa M. Lawson 26 Apr '13

26 Apr '13

Dushyant Arora will present his MSE thesis talk on Friday May 3 at 11:30 AM in Room 302 (note room!). The members of his committee are; Jennifer Rexford, advisor and Michael Freedman, reader. Everyone is invited to attend his talk. His abstract follows below. ------------------- PARIS: ProActive Routing in Scalable Data Centers Modern data centers must meet many challenges and expectations: (a) They must scale to a large number of servers, while offering high bisection bandwidth and flexible placement of virtual machines. (b) They must allow tenants to specify network policies and realize it by forwarding traffic through desired sequences of middleboxes. (c) They must allow tenants to bring their own IP address space to the cloud to ease transition of enterprise applications and middlebox configuration. The traditional approach of connecting layer-two pods through a layer-three core constrains VM placement. More recent "flat" designs are more flexible, but have scalability limitations due to flooding/broadcasting or querying directories of VM locations. Rather than reactively learn VM locations, our PARIS architecture has a controller that pre-positions IP forwarding entries in the switches. Switches within a pod have complete information about the VMs beneath them, while each core switch maintains complete forwarding state for part of the address space. PARIS offers network designers the flexibility to choose a topology that meets their latency and bandwidth requirements. PARIS also allows tenants to bring their own IP address space and utilizes lightweight virtualization using Linux containers to offer middlebox service in a manner that truly reflects the pay-as-you go model of cloud computing. It utilizes MPLS label forwarding and aggregation in the network core and uses source routing at the network edge to realize middlebox policies specified by tenants. Finally, we evaluate our prototype implementation built using Openflow-compliant switches and NOX controller.

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S Sen FPO
by Melissa M. Lawson 26 Apr '13

26 Apr '13

Siddhartha Sen will present his FPO on Wednesday May 1 at 1PM in Room 401 (note room!). The members of his committee are: Bob Tarjan and Michael Freedman, co-advisors; Michael Freedman and Jennifer Rexford readers; Vivek Pai and Bob Sedgewick, nonreaders. A copy of his thesis, "New Systems and Algorithms for Scalable Fault Tolerance", is on display in Room 310. Everyone is invited to attend his talk.

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Nayden Nedev MSE thesis talk
by Melissa M. Lawson 25 Apr '13

25 Apr '13

Nayden Nedev will present his MSE thesis talk on Thursday May 2 at 1PM in Room 401 (note room!). The members of his committee are: David Walker, advisor, and Jennifer Rexford, reader. Everyone is invited to attend his talk. His abstract follows below. ------------------------------------------------- Title: Parallel Consistent Network Updates Abstract: Network configuration changes are a frequent operation performed by network administrators. Unfortunately, these changes can result in a wide range of problems such as network outages, security vulnerabilities or worse overall network performance. A recent result in this area proposes the notion of consistent network update - an update that preserves certain properties when updating from one network policy to another. The authors of the mentioned work describe a per-packet consistent update algorithm that guarantees that every packet in the network traverses either the old policy or the new one but not some mixture of the two. With the advent of software-defined networking, development of centralized, tightly-coordinated applications with strong global correctness properties has been made possible. However, it is an open problem how to bring more parallelism to these applications and how to leverage general-purpose multicore and multiprocessor machines to improve their performance. In this work, we propose two parallelized versions of the per-packet consistency update mechanism. We implement them on top of Floodlight - a new multi-threaded software-defined networking controller platform. We evaluate their performance on two example applications - a network-wide host location learning and a shortest-path routing application. ----- Original Message -----

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B Kapicioglu FPO
by Melissa M. Lawson 25 Apr '13

25 Apr '13

Berk Kapicioglu will present his FPO on Thursday May 2 at 1:30PM in Room 402. The members of his committee are: Rob Schapire, advisor; David Blei and Tony Jebara (Columbia), readers; Jennifer Rexford and Andrea LaPaugh, nonreaders. A copy of his thesis, "Applications of Machine Learning to Location Data", is on display in Room 310. Everyone is invited to attend his talk.

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W Lloyd FPO
by Melissa M. Lawson 25 Apr '13

25 Apr '13

Wyatt Lloyd will present his FPO on Thursday May 2 at 10AM in Room 402. The members of his committee are: Michael Freedman, advisor; Vivek Pai and David Andersen (CMU), readers; Jennifer Rexford and Margaret Martonosi, nonreaders. A copy of his thesis, "Stronger Consistency and Semantics for Low-latency Geo-Replicated Storage", is on display in Room 310. Everyone is invited to attend his talk.

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Fwd: thesis info
by Melissa M. Lawson 25 Apr '13

25 Apr '13

Arpan Ghosh will present his MSE thesis talk on Wednesday May 1 at 3PM in Room 301 (note room!). the members of his committee are: Mung Chiang, ELE (advisor) and Andrea LaPaugh (reader). Everyone is invited to attend his talk. His abstract follows below. ------------------------------------ Abstract: Tracking the Business Pulse Using Twitter While Twitter surged to popularity soon after its creation, it took a few years to find legitimate & profitable uses for it. Just like it brought fans closer than ever to celebrities, people closer to real-time news and voters closer to presidential candidates, today it is helping define a new paradigm for consumer businesses to interact with their past, present and future customers. Twitter makes it very easy for businesses to directly ‘reach-out’ to the customers that follow them, for the purposes of announcements, promotions and advertising. The return path of the communication loop wherein a company would like to analyze customer needs, sentiment, feedback, reviews and grievances, is much harder for several reasons. Twitter as a data stream is very sparse and has a low signal to noise ratio as it continues to be dominated by tweets that are basically about nothing: personal conversations, random observations or spam. It is a slight exaggeration to classify tweets as semi-structured data, even with the presence of hashtags, due to the dynamic method of Hashtag creation and their longevity. Twitter also provides very sparse information about the users authoring tweets. This work is driven by the vision of building a tool that allows businesses to monitor, analyze and gain insights, in near real-time, of the opinion, sentiment and feedback that exists about them on social networks like twitter, analogous to what Google finance accomplishes for the financial aspect of businesses. To this end we make the following contributions: 1) A quantitative analysis of twitter usage to determine its suitability for this business-oriented use case. 2) A classifier filter out ‘irrelevant’ tweets for the aforementioned use-case. 3) An algorithm to detect trending increased activity on twitter pertaining to a business and cluster periods of high activity into logically separable stories/events in the business’ timeline. 4) An algorithm to classify people talking about a business on twitter based on their expertise/influence in the area/topic that the business specializes in.

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EE Seminar - May 13, 2013, 12:30 pm, E-Quad B205 - Dr. Simon Moore
by Nicole E. Wagenblast 25 Apr '13

25 Apr '13

SeminarLogo.jpg Speaker: Dr. Simon Moore University of Cambridge Title: Does Rigorous Computer Systems Research Demand Open Source Hardware? Date: Monday, May 13, 2013 Time: 12:30 p.m. (Light lunch will be served.) Room: E-Quad, Room B205 Host: Prof. Ruby Lee Abstract: Computer systems research relies heavily on open source software like the LLVM compiler framework, operating systems like FreeBSD and Linux, para virtualisation like Xen, etc. However, much of this research is bounded by the availability of commodity hardware which provides an unnecessary fixed point in the design space exploration process. In this talk I argue that we need more open source and rigorously engineered hardware platforms to facilitate computer systems research which straddles traditional boundaries. To illustrate the point, the CHERI processor (a 64-bit RISC based capability machine soon to be open sourced) will be introduced together with observations from associated compilation (LLVM based) and operating system (FreeBSD based) research into fine grained sand boxing. By making changes all the way from the gate-level to the application-level we believe that much more secure computer systems can be constructed whilst providing a migration path for legacy systems. Bio: Simon Moore is Reader (Associate Professor in USA terms) in Computer Architecture at the University of Cambridge Computer Laboratory in England, where he undertakes research and teaching in the general area of computer design with particular interests in massively parallel secure computer architecture. Dr. Moore is the senior member of the Computer Architecture research group < http://www.cl.cam.ac.uk/research/comparch/ >. This work was undertaken in collaboration with SRI International. Portions of this work were sponsored by the Defense Advanced Research Projects Agency (DARPA) and the Air Force Research Laboratory (AFRL), under contract FA8750-10-C-0237. The views, opinions, and/or findings contained in this report are those of the author and should not be interpreted as representing the official views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense.

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Seminar: Prof. Josep Torrellas, UIUC. Tuesday April 30.
by Margaret Martonosi 25 Apr '13

25 Apr '13

Hello-- Prof. Josep Torrellas from UIUC will be visiting Princeton and giving a seminar on Tuesday April 30. The seminar will be from 12:30-1:30 in CS Room 302, with pizza beforehand starting at noon. Title/abstract below. I have reserved a 1-hour slot for him to meet with grad students from 2:30-3:30pm that day. That will occur in CS room 401. If you are interested in a one-on-one slot with Josep, please email me---he has a couple morning slots still available. Thanks, Margaret ----------------------------------------------------------------- Toward Programmable High-Performance Multicores Josep Torrellas University of Illinois, Urbana-Champaign http://iacoma.cs.uiuc.edu/~torrellas One of the biggest challenges facing us today is how to design parallel architectures that attain high performance while efficiently supporting a programmable environment. In this talk, I describe novel organizations that will make the next generation of multicores more programmable and higher performance. Specifically, I show how to automatically reuse the upcoming transactional memory hardware for optimized code generation. Next, I describe a prototype of Record&Replay hardware that brings program monitoring for debugging and security to the next level of capability. I also describe a new design of hardware fences that is overhead-free and requires no software support. Finally, if time permits, I will outline architectural support to detect sequential consistency violations transparently. BIO: Josep Torrellas is a Professor of Computer Science and Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign (UIUC). He is a Fellow of IEEE and ACM. He is the Director of the Center for Programmable Extreme-Scale Computing, a center funded by DARPA, DOE, and NSF that focuses on architectures for extreme energy and power efficiency. He also directs the Intel-Illinois Parallelism Center (I2PC), a center created by Intel to advance parallel computing in clients. He has made contributions to parallel computer architecture in the areas of shared-memory multiprocessor organizations, cache hierarchies and coherence protocols, thread-level speculation, and hardware and software reliability. He received a Ph.D. from Stanford University. ------------------------------------------------------------ Margaret Martonosi Hugh Trumbull Adams '35 Professor of Computer Science Princeton University http://www.princeton.edu/~mrm mrm(a)princeton.edu

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V Kim FPO
by Melissa M. Lawson 24 Apr '13

24 Apr '13

Vladimir Kim will present his FPO on Wednesday May 1 at 4PM in Room 302 (note room!). The members of his committee are: Tom Funkhouser, advisor; Szymon Rusinkiewicz and Wilmot Li (Adobe), readers; David Dobkin and Adam Finkelstein, nonreaders. A copy of his thesis, "Understanding the Structure of Large, Diverse Collections of Shapes", is on display in Room 310. Everyone is invited to attend his talk.

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