- talks - lists.cs.princeton.edu

TODAY at 4:30pm in B205 E-Quad - Suriya Gunasekar, Toyota Technological Institute at Chicago
by Emily Lawrence 11 Feb '19

11 Feb '19

Speaker: Suriya Gunasekar, Toyota Technological Institute at Chicago Title: Rethinking the Role of Optimization in Learning Day: Monday, February 11, 2019 Time: 4:30 pm Room: B205 Engineering Quadrangle Host: Prof. Peter Ramadge Abstract: In this talk, I will overview our recent progress towards understanding how we learn large capacity machine learning models, … [View More]

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Zvi Galil Distinguished Lecture next Thursday (Valentine's Day) 12:30p
by Nick Feamster 07 Feb '19

07 Feb '19

Folks, Zvi Galil, Dean of Computing at Georgia Tech, the architect of the online MS in Computer Science at Georgia Tech, former Dean of Columbia, former president of Tel Aviv University, and member of the NAE, will be joining us next week for a distinguished lecture to tell us about Georgia Tech’s online Masters in Computer Science (OMSCS). Our department can learn a lot from Zvi and his OMSCS adventure, which I helped start (I developed one of the first courses in the degree). Aside from … [View More]

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Colloquium Speaker-Tam Vu, TODAY at 4:30pm
by Emily C. Lawrence 07 Feb '19

07 Feb '19

Colloquium Speaker Tam Vu from the University of Colorado, Boulder Thursday, February 7 - 4:30-5:30pm Computer Science - Room 105 Host: Jennifer Rexford " Earable Computers : Ear-worn Systems for Healthcare, HCI, BCI, and Brain Stimulations" This talk introduces the concept of " Earable computers", small computing and actuating devices that are worn inside, behind, around, or on user's ears. Earable sensing and actuation are motivated from the fact that human ears are relatively … [View More]

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Reminder: Colloquium Speaker-Tam Vu, tomorrow at 4:30pm
by Emily C. Lawrence 06 Feb '19

06 Feb '19

Colloquium Speaker Tam Vu from the University of Colorado, Boulder Thursday, February 7 - 4:30-5:30pm Computer Science - Room 105 Host: Jennifer Rexford " Earable Computers : Ear-worn Systems for Healthcare, HCI, BCI, and Brain Stimulations" This talk introduces the concept of " Earable computers", small computing and actuating devices that are worn inside, behind, around, or on user's ears. Earable sensing and actuation are motivated from the fact that human ears are relatively … [View More]

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Robert Harrison will present his Pre FPO on February 7, 2019 at 2pm in CS 402
by Nicki Gotsis 04 Feb '19

04 Feb '19

Robert Harrison will present his Pre FPO on February 7, 2019 at 2pm in CS 402. The members of his committee are as follows: Jennifer Rexford (adviser), Nick Feamster, Nate Foster (Cornell), Kyle Jamieson, and David Walker All are welcome to attend. The talk title and abstract follow below. Title: Scalable Network-Wide Telemetry with Programmable Switches Abstract: Managing and securing modern networks requires collecting and analyzing network traffic from a distributed collection of … [View More]switches in real time, i.e., performing network-wide telemetry. Telemetry systems must be flexible and fine-grained, both in timescale and traffic detail, to support the wide range of queries that analyze security, performance, and reliability properties of networks. Yet, they must also scale as the number of monitoring tasks, link speeds, and the size of the networks grow. Achieving fine-grained, network-wide telemetry that scales requires balancing the division of labor between high-speed network switches and general-purpose CPUs. Modern Protocol Independent Switch Architecture (PISA) switches combine the high-speed processing of network hardware with the programmability, albeit limited, of general-purpose CPUs and allow us to adjust this division of labor. This thesis explores, first, how to partition telemetry tasks between a general-purpose CPU and a single PISA switch for a flexible query language, and second, how to distribute a subset of queries expressed in that language across a set of switches. In order to realize these goals, we must address two key challenges: (i) how to effectively use a programmable switch to perform customized data collection that minimizes the amount of data processed by the CPU, and (ii) how to efficiently coordinate among a distributed set of switches to compute the output of a global function. In addressing both of these challenges, we must operate within memory, processing, and bandwidth constraints. We describe our solutions, respectively, to these challenges below. First, we present Sonata, an expressive and scalable network telemetry system that performs the collection and analysis of network traffic using the compute resources of both stream-processing servers and a programmable switch. Sonata provides a declarative interface to express queries using dataflow operators for a range of common telemetry tasks. Sonata partitions queries across a stream processor and a switch data plane, running as much of the query as it can on the network switch at line rate. Sonata models the constraints of PISA switches and solves an optimization problem to compile the high-level dataflow operators in the query language to low-level PISA primitives. Sonata can support a wide range of monitoring tasks while reducing the workload on the stream processor by orders of magnitude compared to existing telemetry systems. Second, we present Herd, a system for implementing a subset of Sonata queries distributed across a set of switches with high accuracy under resource constraints. Our solution counts relevant flows at distributed switches without maintaining per-flow state and probabilistically reports them to a central coordinator. Based on these reports, the coordinator adapts the reporting threshold and probability at each switch based on the spatial locality of the flows. Simulations using real traffic traces show that our prototype can detect network-wide heavy hitters accurately with 17% savings in communication overhead and 38% savings in switch state compared to existing approaches. We then present an algorithm to tune system parameters in order to maximize detection accuracy under resource constraints. Together, Sonata and Herd provide network operators the ability to execute a set of network-wide telemetry queries from a single interface that combines the strengths of both programmable data planes and general-purpose CPUs to achieve both flexibility and scalability. [View Less]

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Colloquium Speaker-Cynthia Sturton, TODAY at 12:30
by Emily C. Lawrence 04 Feb '19

04 Feb '19

Colloquium Speaker Cynthia Sturton, from University of North Carolina at Chapel Hill Monday, February 4 - 12:30pm Computer Science - Room 105 Host: Margaret Martonosi “Hardware is the New Software: Finding Exploitable Bugs in Hardware Designs” Bugs in hardware designs can create vulnerabilities that open the machine to malicious exploit. Despite mature functional validation tools and new research in designing secure hardware, the question of how to find and recognize those bugs … [View More]

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Reminder: Colloquium Speaker-Cynthia Sturton, tomorrow at 12:30
by Emily C. Lawrence 03 Feb '19

03 Feb '19

Colloquium Speaker Cynthia Sturton, from University of North Carolina at Chapel Hill Monday, February 4 - 12:30pm Computer Science - Room 105 Host: Margaret Martonosi “Hardware is the New Software: Finding Exploitable Bugs in Hardware Designs” Bugs in hardware designs can create vulnerabilities that open the machine to malicious exploit. Despite mature functional validation tools and new research in designing secure hardware, the question of how to find and recognize those bugs … [View More]

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Colloquium Speaker-Tam Vu, Thursday, Feb 7
by Emily C. Lawrence 01 Feb '19

01 Feb '19

Colloquium Speaker Tam Vu from the University of Colorado, Boulder Thursday, February 7 - 4:30-5:30pm Computer Science - Room 105 Host: Jennifer Rexford " Earable Computers : Ear-worn Systems for Healthcare, HCI, BCI, and Brain Stimulations" This talk introduces the concept of " Earable computers", small computing and actuating devices that are worn inside, behind, around, or on user's ears. Earable sensing and actuation are motivated from the fact that human ears are relatively … [View More]

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Colloquium Speaker-Cynthia Sturton, Monday, Feb 4
by Emily C. Lawrence 29 Jan '19

29 Jan '19

Colloquium Speaker Cynthia Sturton , from University of North Carolina at Chapel Hill Monday, February 4- 12:30pm Computer Science - Room 105 “Hardware is the New Software: Finding Exploitable Bugs in Hardware Designs” Bugs in hardware designs can create vulnerabilities that open the machine to malicious exploit. Despite mature functional validation tools and new research in designing secure hardware, the question of how to find and recognize those bugs remains open. My students … [View More]

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Mina Tahmasbi Arashloo will present her Pre FPO "Stateful Programming of High-Speed Network Hardware" on Monday, February 4, 2019 at 3pm in CS 302.
by Nicki Gotsis 28 Jan '19

28 Jan '19

Mina Tahmasbi Arashloo will present her Pre FPO "Stateful Programming of High-Speed Network Hardware" on Monday, February 4, 2019 at 3pm in CS 302. The members of her committee are as follows: Jennifer Rexford (adviser); Readers: David Walker, Arvind Krishnamurthy; Examiners: Nick Feamster, Mike Freedman Everyone is invited to attend her talk. The talk title and abstract follow below. Title: Stateful Programming of High-Speed Network Hardware Abstract: Traditionally, network hardware, … [View More]i.e. switches inside the network and Network Interface Cards (NICs) at the end hosts, have been fixed-function ASICs, performing simple stateless packet processing. Stateful packet processing, on the other hand, was mostly implemented in software in the higher layers of the network stack at the end hosts. Today, with link speeds increasing to 100Gbps and beyond, the CPU cost of software packet processing is becoming prohibitive. That, together with the need for network-enforced reliability, security, and efficiency, are forcing more complex, stateful packet processing functionality to be implemented in hardware in network switches and NICs. Moreover, there is an increasing need for programmable network hardware, as opposed to fixed-function ASICs, to enable networks to adapt to the rapidly evolving requirements of online services. Designing programmable network hardware with support for stateful packet processing at high-speed is notoriously difficult. At today’s link speeds, network switches and NICs should transmit a packet every few nanoseconds. However, stateful packet processing reduces opportunities for parallel computation by creating dependencies between operations across packets, and supporting programmability reduces opportunities for protocol-specific optimizations, both making it challenging to keep up with line-rate. Moreover, the need for high speed has kept the programming interfaces of current programmable network hardware quite low-level and only suitable for specifying the behavior of a single device. Thus, programming collections of stateful network devices to realize a local or network-wide functionality efficiently and correctly is known to be extremely difficult and error-prone. This thesis focuses on the design and programming of high-speed stateful network hardware, both at the end hosts and inside the network. At the end host, the transport layer is the most complicated and stateful component of the network stack that is pushed into the NIC’s hardware and is currently implemented as a fixed-function ASIC. We propose Tonic, a programmable hardware architecture for running transport protocols at 100Gbps. At such speed, the transport layer must generate a data segment every few nanoseconds using only a few kilobits of per-flow state, due to the limited memory on the NIC. The per-flow state can potentially be updated by multiple concurrent transport events every few nanoseconds, making it challenging to process them at line rate. As a result, we decompose transport-protocol functionality into operations that must affect the transmission of each packet and those that can safely run at microsecond timescales, hence enabling optimizations for the former. Moreover, by identifying common patterns across transport protocols, we offer programmers a simple API while further optimizing Tonic’s design. Experiments with our FPGA-based prototype show that Tonic can support a wide range of transport protocols and meet timing for 100 Gbps of back-to-back 128-byte packets. To facilitate network-wide stateful packet processing, we propose SNAP, a programming language that abstracts the entire network as “one big stateful switch”. Using SNAP, network operators can develop programs that contain reads and writes to global, persistent arrays, to implement a broad range of in-network applications, from stateful firewalls to fine-grained traffic monitoring. The SNAP compiler takes care of distribution, placement, and optimization of access to these stateful arrays. More specifically, the compiler discovers read/write dependencies between arrays and translates one-big-switch programs into an efficient internal representation based on a variant of binary decision diagrams. This internal representation is used to construct a mixed-integer linear program, which jointly optimizes the placement of state and the routing of traffic across the underlying physical topology. The internal representation is also used to derive the primitive stateful operations required in programmable switches to support SNAP’s network-wide abstractions. All in all, Tonic’s modular interface and SNAP’s one-big-stateful-switch abstraction relieve programmers from dealing with the low-level details of stateful programming of high-speed network hardware throughout the entire network. [View Less]

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