- talks - lists.cs.princeton.edu

Reminder: Colloquium Speaker-Tam Vu, tomorrow at 4:30pm
by Emily C. Lawrence 06 Feb '19

06 Feb '19

Colloquium Speaker Tam Vu from the University of Colorado, Boulder Thursday, February 7 - 4:30-5:30pm Computer Science - Room 105 Host: Jennifer Rexford " Earable Computers : Ear-worn Systems for Healthcare, HCI, BCI, and Brain Stimulations" This talk introduces the concept of " Earable computers", small computing and actuating devices that are worn inside, behind, around, or on user's ears. Earable sensing and actuation are motivated from the fact that human ears are relatively close to the sources of many important physiological signals such as the brain, eyes, facial muscles, heart, core body temperature, and more. Therefore, placing the sensors and associated stimulators inside the ear canals or behind the ears could open up a wide range of applications from improving cognitive function, keeping truck drivers from falling asleep while driving, extending attention span, to quantifying pain and suffering, reducing opioid use, suppressing seizure, just to name a few. This talk will discuss the opportunities that earable systems could bring and system challenges that need to be addressed to unleash its potentials. I will share our experience and lessons learned through realizing such systems in the context of human computer interaction, brain computer interaction, and healthcare. Bio: Tam Vu is an Assistant Professor of Computer Science Department at University of Colorado, Boulder. He directs Mobile and Networked Systems (MNS) Lab at the university, where he and his team conduct system research in the areas of wearable and mobile systems including mobile healthcare, mobile security, cyber physical system, and wireless sensing. His research has been recognized with a NSF CAREER award, two Google Faculty Awards, ten best paper awards, best paper nomination, and research highlights in flagship venues in mobile system research including MobiCom , MobiSys , and SenSys . He is also actively pushing his research outcomes to practice through technology transfer activities with 17 patents filed and leading two start-ups that he co-founded to commercialize them.

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Robert Harrison will present his Pre FPO on February 7, 2019 at 2pm in CS 402
by Nicki Gotsis 04 Feb '19

04 Feb '19

Robert Harrison will present his Pre FPO on February 7, 2019 at 2pm in CS 402. The members of his committee are as follows: Jennifer Rexford (adviser), Nick Feamster, Nate Foster (Cornell), Kyle Jamieson, and David Walker All are welcome to attend. The talk title and abstract follow below. Title: Scalable Network-Wide Telemetry with Programmable Switches Abstract: Managing and securing modern networks requires collecting and analyzing network traffic from a distributed collection of switches in real time, i.e., performing network-wide telemetry. Telemetry systems must be flexible and fine-grained, both in timescale and traffic detail, to support the wide range of queries that analyze security, performance, and reliability properties of networks. Yet, they must also scale as the number of monitoring tasks, link speeds, and the size of the networks grow. Achieving fine-grained, network-wide telemetry that scales requires balancing the division of labor between high-speed network switches and general-purpose CPUs. Modern Protocol Independent Switch Architecture (PISA) switches combine the high-speed processing of network hardware with the programmability, albeit limited, of general-purpose CPUs and allow us to adjust this division of labor. This thesis explores, first, how to partition telemetry tasks between a general-purpose CPU and a single PISA switch for a flexible query language, and second, how to distribute a subset of queries expressed in that language across a set of switches. In order to realize these goals, we must address two key challenges: (i) how to effectively use a programmable switch to perform customized data collection that minimizes the amount of data processed by the CPU, and (ii) how to efficiently coordinate among a distributed set of switches to compute the output of a global function. In addressing both of these challenges, we must operate within memory, processing, and bandwidth constraints. We describe our solutions, respectively, to these challenges below. First, we present Sonata, an expressive and scalable network telemetry system that performs the collection and analysis of network traffic using the compute resources of both stream-processing servers and a programmable switch. Sonata provides a declarative interface to express queries using dataflow operators for a range of common telemetry tasks. Sonata partitions queries across a stream processor and a switch data plane, running as much of the query as it can on the network switch at line rate. Sonata models the constraints of PISA switches and solves an optimization problem to compile the high-level dataflow operators in the query language to low-level PISA primitives. Sonata can support a wide range of monitoring tasks while reducing the workload on the stream processor by orders of magnitude compared to existing telemetry systems. Second, we present Herd, a system for implementing a subset of Sonata queries distributed across a set of switches with high accuracy under resource constraints. Our solution counts relevant flows at distributed switches without maintaining per-flow state and probabilistically reports them to a central coordinator. Based on these reports, the coordinator adapts the reporting threshold and probability at each switch based on the spatial locality of the flows. Simulations using real traffic traces show that our prototype can detect network-wide heavy hitters accurately with 17% savings in communication overhead and 38% savings in switch state compared to existing approaches. We then present an algorithm to tune system parameters in order to maximize detection accuracy under resource constraints. Together, Sonata and Herd provide network operators the ability to execute a set of network-wide telemetry queries from a single interface that combines the strengths of both programmable data planes and general-purpose CPUs to achieve both flexibility and scalability.

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Colloquium Speaker-Cynthia Sturton, TODAY at 12:30
by Emily C. Lawrence 04 Feb '19

04 Feb '19

Colloquium Speaker Cynthia Sturton, from University of North Carolina at Chapel Hill Monday, February 4 - 12:30pm Computer Science - Room 105 Host: Margaret Martonosi “Hardware is the New Software: Finding Exploitable Bugs in Hardware Designs” Bugs in hardware designs can create vulnerabilities that open the machine to malicious exploit. Despite mature functional validation tools and new research in designing secure hardware, the question of how to find and recognize those bugs remains open. My students and I have developed two tools in response to this question. The first is a security specification miner; it semi-automatically identifies security-critical properties of a design specified at the register transfer level. The second tool, Coppelia , is a symbolic execution engine that explores a hardware design and generates complete exploits for the security bugs it finds. We use Coppelia and our set of generated security properties to find new bugs in the open-source RISC-V and OR1k CPU architectures. Bio: Cynthia Sturton is an Assistant Professor and Peter Thacher Grauer Fellow at the University of North Carolina at Chapel Hill. She leads the Hardware Security @ UNC research group to investigate the use of static and dynamic analysis to protect against vulnerable hardware designs. Her research is funded by several National Science Foundation awards, the Semiconductor Research Corporation, Intel, a Junior Faculty Development Award from the University of North Carolina, and a Google Faculty Research Award. She was recently awarded the Computer Science Departmental Teaching Award at the University of North Carolina. Sturton received her B.S.E. from Arizona State University and her M.S. and Ph.D. from the University of California, Berkeley. Lunch will be available to talk attendees at 12:00pm.

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Reminder: Colloquium Speaker-Cynthia Sturton, tomorrow at 12:30
by Emily C. Lawrence 03 Feb '19

03 Feb '19

Colloquium Speaker Cynthia Sturton, from University of North Carolina at Chapel Hill Monday, February 4 - 12:30pm Computer Science - Room 105 Host: Margaret Martonosi “Hardware is the New Software: Finding Exploitable Bugs in Hardware Designs” Bugs in hardware designs can create vulnerabilities that open the machine to malicious exploit. Despite mature functional validation tools and new research in designing secure hardware, the question of how to find and recognize those bugs remains open. My students and I have developed two tools in response to this question. The first is a security specification miner; it semi-automatically identifies security-critical properties of a design specified at the register transfer level. The second tool, Coppelia , is a symbolic execution engine that explores a hardware design and generates complete exploits for the security bugs it finds. We use Coppelia and our set of generated security properties to find new bugs in the open-source RISC-V and OR1k CPU architectures. Bio: Cynthia Sturton is an Assistant Professor and Peter Thacher Grauer Fellow at the University of North Carolina at Chapel Hill. She leads the Hardware Security @ UNC research group to investigate the use of static and dynamic analysis to protect against vulnerable hardware designs. Her research is funded by several National Science Foundation awards, the Semiconductor Research Corporation, Intel, a Junior Faculty Development Award from the University of North Carolina, and a Google Faculty Research Award. She was recently awarded the Computer Science Departmental Teaching Award at the University of North Carolina. Sturton received her B.S.E. from Arizona State University and her M.S. and Ph.D. from the University of California, Berkeley. Lunch will be available to talk attendees at 12:00pm.

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Colloquium Speaker-Tam Vu, Thursday, Feb 7
by Emily C. Lawrence 01 Feb '19

01 Feb '19

Colloquium Speaker Tam Vu from the University of Colorado, Boulder Thursday, February 7 - 4:30-5:30pm Computer Science - Room 105 Host: Jennifer Rexford " Earable Computers : Ear-worn Systems for Healthcare, HCI, BCI, and Brain Stimulations" This talk introduces the concept of " Earable computers", small computing and actuating devices that are worn inside, behind, around, or on user's ears. Earable sensing and actuation are motivated from the fact that human ears are relatively close to the sources of many important physiological signals such as the brain, eyes, facial muscles, heart, core body temperature, and more. Therefore, placing the sensors and associated stimulators inside the ear canals or behind the ears could open up a wide range of applications from improving cognitive function, keeping truck drivers from falling asleep while driving, extending attention span, to quantifying pain and suffering, reducing opioid use, suppressing seizure, just to name a few. This talk will discuss the opportunities that earable systems could bring and system challenges that need to be addressed to unleash its potentials. I will share our experience and lessons learned through realizing such systems in the context of human computer interaction, brain computer interaction, and healthcare. Bio: Tam Vu is an Assistant Professor of Computer Science Department at University of Colorado, Boulder. He directs Mobile and Networked Systems (MNS) Lab at the university, where he and his team conduct system research in the areas of wearable and mobile systems including mobile healthcare, mobile security, cyber physical system, and wireless sensing. His research has been recognized with a NSF CAREER award, two Google Faculty Awards, ten best paper awards, best paper nomination, and research highlights in flagship venues in mobile system research including MobiCom , MobiSys , and SenSys . He is also actively pushing his research outcomes to practice through technology transfer activities with 17 patents filed and leading two start-ups that he co-founded to commercialize them.

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Colloquium Speaker-Cynthia Sturton, Monday, Feb 4
by Emily C. Lawrence 29 Jan '19

29 Jan '19

Colloquium Speaker Cynthia Sturton , from University of North Carolina at Chapel Hill Monday, February 4- 12:30pm Computer Science - Room 105 “Hardware is the New Software: Finding Exploitable Bugs in Hardware Designs” Bugs in hardware designs can create vulnerabilities that open the machine to malicious exploit. Despite mature functional validation tools and new research in designing secure hardware, the question of how to find and recognize those bugs remains open. My students and I have developed two tools in response to this question. The first is a security specification miner; it semi-automatically identifies security-critical properties of a design specified at the register transfer level. The second tool, Coppelia , is a symbolic execution engine that explores a hardware design and generates complete exploits for the security bugs it finds. We use Coppelia and our set of generated security properties to find new bugs in the open-source RISC-V and OR1k CPU architectures. Bio: Cynthia Sturton is an Assistant Professor and Peter Thacher Grauer Fellow at the University of North Carolina at Chapel Hill. She leads the Hardware Security @ UNC research group to investigate the use of static and dynamic analysis to protect against vulnerable hardware designs. Her research is funded by several National Science Foundation awards, the Semiconductor Research Corporation, Intel, a Junior Faculty Development Award from the University of North Carolina, and a Google Faculty Research Award. She was recently awarded the Computer Science Departmental Teaching Award at the University of North Carolina. Sturton received her B.S.E. from Arizona State University and her M.S. and Ph.D. from the University of California, Berkeley.

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Mina Tahmasbi Arashloo will present her Pre FPO "Stateful Programming of High-Speed Network Hardware" on Monday, February 4, 2019 at 3pm in CS 302.
by Nicki Gotsis 28 Jan '19

28 Jan '19

Mina Tahmasbi Arashloo will present her Pre FPO "Stateful Programming of High-Speed Network Hardware" on Monday, February 4, 2019 at 3pm in CS 302. The members of her committee are as follows: Jennifer Rexford (adviser); Readers: David Walker, Arvind Krishnamurthy; Examiners: Nick Feamster, Mike Freedman Everyone is invited to attend her talk. The talk title and abstract follow below. Title: Stateful Programming of High-Speed Network Hardware Abstract: Traditionally, network hardware, i.e. switches inside the network and Network Interface Cards (NICs) at the end hosts, have been fixed-function ASICs, performing simple stateless packet processing. Stateful packet processing, on the other hand, was mostly implemented in software in the higher layers of the network stack at the end hosts. Today, with link speeds increasing to 100Gbps and beyond, the CPU cost of software packet processing is becoming prohibitive. That, together with the need for network-enforced reliability, security, and efficiency, are forcing more complex, stateful packet processing functionality to be implemented in hardware in network switches and NICs. Moreover, there is an increasing need for programmable network hardware, as opposed to fixed-function ASICs, to enable networks to adapt to the rapidly evolving requirements of online services. Designing programmable network hardware with support for stateful packet processing at high-speed is notoriously difficult. At today’s link speeds, network switches and NICs should transmit a packet every few nanoseconds. However, stateful packet processing reduces opportunities for parallel computation by creating dependencies between operations across packets, and supporting programmability reduces opportunities for protocol-specific optimizations, both making it challenging to keep up with line-rate. Moreover, the need for high speed has kept the programming interfaces of current programmable network hardware quite low-level and only suitable for specifying the behavior of a single device. Thus, programming collections of stateful network devices to realize a local or network-wide functionality efficiently and correctly is known to be extremely difficult and error-prone. This thesis focuses on the design and programming of high-speed stateful network hardware, both at the end hosts and inside the network. At the end host, the transport layer is the most complicated and stateful component of the network stack that is pushed into the NIC’s hardware and is currently implemented as a fixed-function ASIC. We propose Tonic, a programmable hardware architecture for running transport protocols at 100Gbps. At such speed, the transport layer must generate a data segment every few nanoseconds using only a few kilobits of per-flow state, due to the limited memory on the NIC. The per-flow state can potentially be updated by multiple concurrent transport events every few nanoseconds, making it challenging to process them at line rate. As a result, we decompose transport-protocol functionality into operations that must affect the transmission of each packet and those that can safely run at microsecond timescales, hence enabling optimizations for the former. Moreover, by identifying common patterns across transport protocols, we offer programmers a simple API while further optimizing Tonic’s design. Experiments with our FPGA-based prototype show that Tonic can support a wide range of transport protocols and meet timing for 100 Gbps of back-to-back 128-byte packets. To facilitate network-wide stateful packet processing, we propose SNAP, a programming language that abstracts the entire network as “one big stateful switch”. Using SNAP, network operators can develop programs that contain reads and writes to global, persistent arrays, to implement a broad range of in-network applications, from stateful firewalls to fine-grained traffic monitoring. The SNAP compiler takes care of distribution, placement, and optimization of access to these stateful arrays. More specifically, the compiler discovers read/write dependencies between arrays and translates one-big-switch programs into an efficient internal representation based on a variant of binary decision diagrams. This internal representation is used to construct a mixed-integer linear program, which jointly optimizes the placement of state and the routing of traffic across the underlying physical topology. The internal representation is also used to derive the primitive stateful operations required in programmable switches to support SNAP’s network-wide abstractions. All in all, Tonic’s modular interface and SNAP’s one-big-stateful-switch abstraction relieve programmers from dealing with the low-level details of stateful programming of high-speed network hardware throughout the entire network.

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Maciej Halber will present his Pre FPO on Monday, January 28, 2019 at 11am in CS 301.
by Nicki Gotsis 23 Jan '19

23 Jan '19

Maciej Halber will present his Pre FPO on Monday, January 28, 2019 at 11am in CS 301. The members of his committee members are as follows: Thomas Funkhouser (adviser), Adam Finkelstein, Olga Russakovsky, Matthias Niessner (Technical University of Munich), and Szymon Rusinkiewicz Everyone is invited to attend his talk. The talk title and abstract follow below: Title: RGBD Pipeline for 3D Indoor Scene Understanding Abstract: RGBD cameras, devices capable of capturing both color and distance information have became a standard data acquisition device for many computer vision tasks. While providing especially valuable source of data for applications like 3D reconstruction and understanding, pipelines able to solve such problems are complex systems and come with a wide range of new challenges. In this talk, I will present my work on improving several stages of such RGBD pipeline. First, I discuss issues that arise when capturing the data with a commodity RGBD camera, alongside a calibration method to improve it. Second, I describe a method for robustly recovering camera poses from a RGBD video sequence, where I introduce a novel optimization strategy which allows for effective incorporation of man-made priors. Finally, I discuss an algorithm for transferring information between 3D reconstructions of indoor scenes captured at different times, with applications in instance and semantic segmentation.

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Distinguished Colloquium-Larry Peterson TODAY at 2:00pm
by Emily C. Lawrence 23 Jan '19

23 Jan '19

Title: Democratizing the Network Edge Speaker: Larry Peterson, Princeton University and Open Networking Foundation Date/time: 2-3pm Wed Jan 23 Location: CS 105 (the “small auditorium”) Abstract: The network edge—where the access networks that connect homes, businesses, and mobile users to the Internet are implemented—is in the midst of a transformation. Network operators ( Telcos and CableCos ) are transitioning from closed and proprietary hardware to disaggregated and virtualized software running on white-box servers, switches, and access devices. This transformation is partly motivated by the CAPEX savings that come from replacing purpose-built appliances with commodity hardware, but it is mostly driven by the need to increase feature velocity through the softwarization of the access network. The goal is to enable new classes of edge services—e.g., Autonomous Vehicles, Internet-of-Things ( IoT ), Immersive User Interfaces—that benefit from low latency connectivity. This is all part of the growing trend to move functionality to the network edge. This transformation faces two technical challenges. The first is to disaggregate and virtualize existing hardware appliances. This is done, for example, by applying SDN principles (decoupling the network control and data planes) and by breaking monolithic applications into a set of micro-services. The second is to integrate the resulting disaggregated components back into a functioning system, packaged with sufficient configuration and life cycle management tools to make it deployable in a production environment. This talk describes CORD, a community-based open source effort to address these challenges. CORD is being deployed in Telco field trials, but more interestingly, it lowers the barrier for anyone (not just global carriers) to deploy edge solutions that incorporate the latest 5G (wireless) and XGS-PON (fiber) access technologies. The talk concludes with some remarks on the opportunity this democratization of the network edge opens for the research community. Bio: Larry Peterson is the Robert E. Kahn Professor of Computer Science, Emeritus at Princeton University, where he served as Chair from 2003-2009. He is a co-author of the best-selling networking textbook Computer Networks: A Systems Approach (5e). His research focuses on the design, implementation, and deployment of Internet-scale distributed systems, including the widely used PlanetLab and MeasurementLab platforms. He is currently working on a new access edge cloud called CORD, an open source project of the Open Networking Foundation.

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Joshua Wetzel will present his FPO, "Structure-aware Approaches for Deciphering Sequence-specific Protein-DNA Interactions" on Tuesday, 1/29/2019 at 1PM in CS 402.
by Nicki Gotsis 22 Jan '19

22 Jan '19

Joshua Wetzel will present his FPO, "Structure-aware Approaches for Deciphering Sequence-specific Protein-DNA Interactions" on Tuesday, 1/29/2019 at 1PM in CS 402. The members of his committee are: Examiners: Mona Singh (adviser), Shvartsman (CBE), and Barbara Engelhardt; Readers: Ben Raphael and Olga Troyanskaya Everyone is invited to attend his talk. The talk abstract follows below: Abstract Interactions between proteins and specific genomic loci are critical to the proper functioning of all cells. The ability of a DNA-binding protein (DBP) to distinguish between its target binding sites and other genomic regions is required for a myriad of crucial functions, including transcriptional regulation, meiotic recombination, chromatin remodeling, and genome organization. However, the fundamental relationship between the amino acid sequence of a DBP and its DNA-binding preferences remains largely elusive. High-throughput experimental technologies for detecting protein-DNA interactions have advanced substantially in the past decade and have enabled measurements for thousands of natural and synthetic DBP variants. However, these technologies typically require sophisticated analyses to uncover intrinsic DNA-binding specificities from the measured signals, often have poorly understood noise and sampling profiles, and provide little insight into the underlying mechanism of interaction. Meanwhile, precise co-complex structural data provide great insight into the mechanistic principles guiding interactions between DBPs and their DNA ligands, albeit at substantially lower throughput. These two types of data are complementary but rarely considered in concert. In this dissertation, I describe novel computational approaches that improve the accuracy and interpretability of inferences derived from high-throughput protein-DNA interaction data, via direct consideration of the underlying protein-DNA structural interaction interface shared across proteins within the same DNA-binding family. First, I describe a systematic exploration of the DNA-binding landscape for Cys2His2 zinc finger (C2H2- ZF) proteins, the most abundant DNA-binding family in eukaryotes. Here we inferred the largest set of C2H2-ZF specificities to date and developed a state-of-the-art structurallyinspired method for predicting specificities for novel C2H2-ZFs. Second, I demonstrate how to leverage the large amounts of specificity data available for DBDs to develop a general framework that improves accuracy of high-throughput DNA-binding specificity inferences by jointly considering interaction preferences for groups of proteins from the same DNA-binding family, rewarding global consistency according to an expected similarity measure reflecting family-level structural considerations. Finally, I provide a probabilistic framework for improving interpretability of high-throughput data by mapping inferred specificities of DBPs from the same DNA-binding family onto a common “reference” structural interface model derived from aggregated family-level co-complex data.

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