- talks - lists.cs.princeton.edu

Xiaozhou Li will present his Pre-FPO on 12/9/15 in CS 401 at 10am
by Nicki Gotsis 08 Dec '15

08 Dec '15

Xiaozhou Li will present his Pre-FPO on 12/9/15 in CS 401 at 10am. The members of his committee are: Mike Freedman (adviser), Kyle Jamieson, Michael Kaminsky (Intel Labs), Jennifer Rexford, and Kai Li. Below are the title and abstract of his talk. Title: Towards High-performance and Cost-effective Key-Value Storage Abstract: Key-value storage is one of the fundamental building blocks for today’s large-scale, high-performance data-intensive applications. In this talk, I will present my research on improving the performance and scalability of key-value storage in a cost effective manner, with a particular focus on combining new hardware and infrastructure capabilities with carefully-crafted algorithmic techniques. I will first present the design, implementation, and evaluation of a high-throughput and memory-efficient concurrent hash table. The design arises from careful attention to systems-level optimizations such as minimizing critical section length and reducing interprocessor coherence traffic through algorithm re-engineering. We exploited Intel’s recent hardware transactional memory (HTM) for concurrency control, and found that HTM provides software engineering benefits by reducing the intellectual complexity of locking more than it provides performance benefits. Algorithmic optimizations that benefit both HTM and designs for fine-grained locking are needed to achieve high performance. In the second part of this talk, I will present SwitchKV, a new scalable key-value store system design that combines high-performance cache nodes with resource constrained backend nodes to provide load balancing in the face of unpredictable workload skew. The cache nodes absorb the hottest queries so that no individual backend node is over-burdened. Compared with previous designs, SwitchKV exploits SDN techniques and deeply optimized switch hardware to enable efficient content based routing. Programmable network switches keep track of cached keys and route requests to the appropriate nodes at line speed, based on keys encoded in packet headers. A new hybrid caching strategy keeps cache and switch forwarding rules updated with low overhead and ensures that system load is always well-balanced under rapidly changing workloads. We demonstrate SwitchKV can meet the service-level objectives for many cloud services more efficiently than traditional systems.

1 0

Nanxi Kang will present her FPO, "Flexible Enterprise Network Management on Commodity Switches" on Monday, 12/14/2015 at 3pm - 5pm, 301 COS.
by Nicki Gotsis 07 Dec '15

07 Dec '15

Nanxi Kang will present her FPO, "Flexible Enterprise Network Management on Commodity Switches" on Monday, 12/14/2015 at 3pm - 5pm, 301 COS. The members of her committee are, Jennifer Rexford (adviser), readers: Nicholas Feamster and Sanjay Rao (Purdue University); nonreaders: David Walker and Michael Freedman A copy of her thesis is available in Room 310. Everyone is invited to attend her talk. The talk abstract follows below: Enterprise networks interconnect heterogeneous hosts, requiring careful management to provide secure, reliable and high-performance network communication. Today, the operators have to manually configure individual network devices, while considering the host address assignments and devices constraints (e.g., limited memory). These approaches are too complicated and inefficient for enterprise networks with growing numbers of hosts and devices. The rise of Software Defined Networks (SDN) offers opportunities to simplify the management of enterprise networks. Leveraging the logically-centralized control plane and the programmable switch rule-tables in SDN, we design a novel network management system that supports flexible policies and reduces configuration complexity. We argue that the operators should focus on defining network-wide policies rather than grappling with low-level details, such as switch memory sizes, individual switch configurations and host addresses. It is the controller’s job to compile the high-level policies into rules for individual switches while staying within the rule-table sizes. In this thesis, we present a flexible enterprise network management system that assigns addresses based on host attributes, distributes network-wide policies across multiple switches and computes switch rules to achieve high-level load balancing policies. Specifi-cally, • we propose the “Attribute-Carrying IPs” (ACIPs) abstraction, where the attributes of a host are encoded in the IP addresses to enable flexible policy specification. We present Alpaca, algorithms for realizing ACIPs under practical constraints of limited length IP addresses and constraint switch rule-tables. • we propose the “One Big Switch” abstraction, which consists of an endpoint policy that views all hosts connected to a single switch, a hop-by-hop routing policy that defines paths between endpoints and a compiler that synthesizes switch rules that iii obey policies and adhere to the resource constraints. We present efficient algorithms that distribute policies across networks while managing rule-space constraints. • we propose the “One Big Server” abstraction, where a switch load balances incoming service requests to multiple equivalent servers based on their capacities. We present Niagara, an SDN-based traffic-splitting scheme that achieves accurate traffic splits while being extremely efficient in using the rule-table space.

1 0

Yiming Liu will present his FPO on Wednesday, 12/9/2015 at 10am, 402 Computer Science.
by Nicki Gotsis 02 Dec '15

02 Dec '15

Yiming Liu will present his FPO on Wednesday, 12/9/2015 at 10am, 402 Computer Science. The members of his committee are Szymon Rusinkiewicz (advisor), readers: Aseem Agarwala (Google) and Adam Finkelstein; nonreaders: Jianxiong Xiao and Thomas Funkhouser. A copy of his thesis, is available in Room 310. Everyone is invited to attend his talk. The talk title and abstract follow below: Title: Internet-Data-Driven Image Creation and Enhancement. Traditional systems for image creation and enhancement are completely reliant on user input, either to generate content directly or to evaluate and tune algorithms. The input must be generated by talented artists, and it is applicable only to the image for which it was originally intended. This poses scalability challenges for such traditional image generation and editing systems. An alternative paradigm, which is being researched in a variety of contentgeneration domains, is to exploit the large amount of data made available by users over the Internet. This data may take many forms: images, image keywords, and even judgments about image quality. Although the data is noisy and was not originally intended for the task at hand, it nevertheless serves as a useful source of “prior information.” These priors make it possible to build image creation and enhancement systems that require only a small amount of user input, and do not require the users to be professional artists or designers. This thesis describes three such systems, including low-level image-processing (motion deblurring), high-level editing (keyword-based image stylization), and image creation (sketch-driven iconification). First, by learning based on a massive online user study, we develop a metric for automatically predicting the perceptual quality of images produced by motion deblurring algorithms, without access to the original images. Second, by leveraging online image search engines, we investigate an approach to photo filtering that only requires the user to provide one or more keywords. Third, we develop a system that synthesize a variety of pictograms by remixing portions of icons retrieved from a large online repository.

1 0

Colloquium Speaker- Gillat Kol, Thurs Dec 10, 12:30pm
by Nicole E. Wagenblast 02 Dec '15

02 Dec '15

Colloquium Speaker Gillat Kol, Institute for Advanced Study Thursday, December 10, 12:30pm Computer Science 105 Interactive Information Theory In a profoundly influential 1948 paper, Claude Shannon introduced information theory and used it to study one-way data transmission problems over different channels, both noisy and noiseless. That paper initiated the study of error correcting codes and data compression, two concepts that are especially relevant today with the rise of the internet and data-intensive applications. In the last decades, interactive communication protocols are used and studied extensively, raising the fundamental question: To what extent can Shannon's results be generalized to the interactive setting, where parties engage in an interactive communication protocol? In this talk we will focus on the interactive analog of data compression in an attempt to answer the above question.

1 0

Talk: Arjun Guha, Monday Nov 30, 1:30pm
by Nicole E. Wagenblast 30 Nov '15

30 Nov '15

Talk Arjun Guha, University of Massachusetts, Amherst Monday, November 30, 1:30PM CITP Conference room, 3rd floor Sherrerd Hall A Fast Compiler for NetKAT In the past few years, high-level programming languages have played a key role in several networking platforms, by providing abstractions that streamline application development. Unfortunately, current compilers can take tens of minutes to generate forwarding state for even relatively small networks. This forces programmers to either work around performance issues or revert to using lower-level APIs. In this talk, we first present a new compiler for NetKAT (a network programming language) that is two orders of magnitude faster than existing systems. Our key insight is a new intermediate representation based on a variant of binary decision diagrams that can represent network programs compactly and supports fast, algebraic manipulation. We argue that our compiler scales to large networks using a diverse set of benchmarks. In addition to speed, our new intermediate representation lets us build a powerful new abstraction for network programming. Existing languages provide constructs for programming individual switches, which forces programmers to specify whole-network behavior on a switch-by-switch basis. For the first time, we can compile programs that syntactically represent sets of end-to-end paths through the network. To do so, our compiler automatically inserts stateful operations (e.g., VLAN tagging) to distinguish overlapping paths from each other. Finally, we present a very general implementation of network virtualization that leverages our ability to compile end-to-end paths. The key insight is to give packets two locations--physical and virtual--and synthesize a program that moves packets along physical paths to account for hops in the virtual network. We show that different synthesis strategies can be used to implement global requirements, such as shortest paths, load-balancing, and so on. Arjun Guha is an assistant professor of Computer Science at UMass Amherst. He enjoys tackling problems in systems using the tools and principles of programming languages. Apart from network programming, he has worked on Web security and system configuration languages. He received a PhD in Computer Science from Brown University in 2012 and a BA in Computer Science from Grinnell College in 2006.

1 1

Colloquium Speaker Ran Raz, Mon Nov 30, 12:30pm
by Nicole E. Wagenblast 30 Nov '15

30 Nov '15

Colloquium Speaker Ran Raz, The Weizmann Institute of Science Monday, November 30, 12:30pm Computer Science 105 Delegation of Computation, P-completeness of Linear Programming, and the many facets of the notion of a proof Suppose that Alice performs some computation for Bob, as he does not have sufficient computational power to run the computation himself. Can Bob be convinced that the computation was done correctly? Delegation of Computation is a central problem in modern cryptography. I will describe a recent one-round delegation protocol. The discussion will take us on a journey into the notion of a proof, through some of the most fascinating ideas in the history of theoretical computer science. I will conclude with a seemingly unrelated application to the P-completeness of Linear Programming with a fixed polytope.

1 1

Talk Thomas Wahl, Fri Dec 4- 12:30pm
by Nicole E. Wagenblast 25 Nov '15

25 Nov '15

Thomas Wahl, Northeastern University Friday, December 4, 12:30 - 1:30 PM Computer Science 105 Behavioral Non-Portability in Scientific Numeric Computing The precise semantics of floating-point arithmetic programs depends on the execution platform, including the compiler and the target hardware. Platform dependencies are particularly pronounced for arithmetic-intensive scientific numeric programs and infringe on the highly desirable goal of software portability (which is in fact promised by heterogeneous computing frameworks like OpenCL): the same program run on the same inputs on different platforms can produce different results. So far so bad. Serious doubts on the portability of numeric applications arise when these differences are behavioral, i.e. when they lead to changes in the control flow of a program. In this work I will present an algorithm that takes a numeric procedure and determines an input that is likely to lead to different decisions depending merely on how the arithmetic in the procedure is compiled. Our implementation of the algorithm requires minimal intervention by the user. I will illustrate its operation on examples characteristic of scientific numeric computing, where control flow divergence actually occurs across different execution platforms. Time permitting, I will also sketch how to prove the /absence/ of inputs that may lead to control flow divergence, i.e. how to prove programs /stable/ (in one of the many senses of this word). This is ongoing work. Thomas Wahl is an Assistant Professor at Northeastern University. This is joint work with Yijia Gu, Mahsa Bayati, and Miriam Leeser at Northeastern.

1 0

IEEE SSCS Distinguished Lecture Series at Princeton - Thursday, December 3, 2015 - E-Quad B205
by Nicole E. Wagenblast 25 Nov '15

25 Nov '15

Sent on behalf of Prof. Kaushik Sengupta **Refreshments at 1 pm and a chance to talk with speakers ** cid:image002.png@01D12619.798B8680IEEE SSCS Lehigh/Princeton/Columbia Chapters Present cid:image004.jpg@01D12619.798B8680 Distinguished Lecture Colloquia, December 2015 cid:image005.png@01D12619.798B8680 Speaker: Prof . Jan Van der Spiegel University of Pennsylvania Talk Title : Bio-inspired Polarization Imagers - Making the invisible visible Date: Thursday, December 3, 2015 Time: 1:30 – 2:45 p.m. Location: Princeton University, Department of Electrical Engineering Engineering Quadrangle, Room B205 Olden Street Princeton, NJ 08544 Abstract: Biology provides us with fascinating examples of intelligent, low power, and highly efficient sensory systems. With the advances in CMOS technology, it has become feasible to build microelectronic systems that mimic some of the key features found in biology. This talk will focus on CMOS vision sensors for polarization imaging. We will review briefly the concepts of polarization and how it is used by various species in nature to enhance their vision or to aid with navigation and communication. Inspired by the biology we have explored polarization for a variety of applications to detect features that are hard to see or even invisible to the human eye. More recent results from the literature including the use of polarization imaging for disease detection will be reviewed. Motivated by the potential advantages of polarization imaging, we have developed a CMOS imager that combines the pixel array with micropolarizers and on-chip processing. Details of the design and polarizer optimization will be described. Speaker: Prof . Francesco Svelto, Università di Pavia, Italy Talk Title : On the design of circuits for frequency synthesizers at MM-waves in foto Frankultra scaled CMOS Date: Thursday, December 3, 2015 Time: 3:00 – 4:15 p.m. Location: Princeton University, Department of Electrical Engineering Engineering Quadrangle, Room B205 Olden Street Princeton, NJ 08544 Abstract: Transceivers for wireless communications at millimeter-waves are becoming pervasive in several commercial fields. Taking advantage of a cut-off frequency of hundreds of GHz, CMOS technology is rapidly expanding from Radio Frequency to Millimeter-Waves, thus enabling low-cost compact solutions. The question we raise in this talk is whether scaling is just providing advantages at mm-waves or not. We present experimental data of single devices, comparing 65nm and 32nm nodes in a wide-frequency range. In particular, switches used in VCOs for tank components tuning, MOM and AMOS capacitors, inductors. f T and f MAX increase though slower than in the past, r on *C off , a figure of merit for switches, improves correspondingly. As a consequence, wide-band circuits benefit from scaling to 32nm. As an example, a frequency divider-by-4, based on differential pairs used as dynamic latches, realized in both technology nodes and able to operate up to 108GHz, is discussed. On the contrary, passive components do not improve and eventually degrade their performances. As a consequence, a conventional LC VCO, relying on tank quality factor, is not expected to improve. In this work we discuss a new topology for Voltage Controlled Oscillators, based on inductor splitting, showing low noise and wide tuning range in ultra-scaled nodes. Speaker: Prof. Borivoje Nikolić University of California, Berkeley Talk Title : Resilient, Wide-Voltage-Range RISC-V Processors in 28nm Technologies Borivoje_Nikolic (1)Date: Thursday, December 3, 2015 Time: 4:30 – 5:45 p.m. Location: Princeton University, Department of Electrical Engineering Engineering Quadrangle, Room B205 Olden Street Princeton, NJ 08544 Abstract: This talk presents a design of an energy-efficient microprocessor that implements several techniques for operation in a very wide voltage range. A particular implementation is based on an open Berkeley RISC-V architecture. To enable agile dynamic voltage and frequency scaling, with high energy efficiency the design implements an integrated switched-capacitor DC-DC converter. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read. Architectural resiliency techniques include the use of error correction and dynamic column redundancy. The processor is implemented by using an agile design methodology. Contact Info: Nagi Naganathan, nagisub(a)gmail.com or Kaushik Sengupta, kaushiks(a)princeton.edu

1 0

Yida Wang will present his Pre-FPO on Tuesday, November 24, 2015 at 9am in CS 401
by Nicki Gotsis 17 Nov '15

17 Nov '15

Yida Wang will present his Pre-FPO on Tuesday, November 24, 2015 at 9am in CS 401. The members of his committee are: Kai Li (adviser), Jonathan Cohen (Princeton Neuroscience institute, reader), Nicholas Turk-Browne (Princeton Neuroscience institute, reader), Olga Troyanskaya (non-reader), Sebastian Seung (non-reader). Everyone is invited to attend his talk. The talk title and abstract follow below. Title: Exploring Brain Interactions Using Full Correlation Matrix Analysis Abstract: Functional magnetic resonance imaging (fMRI) measures human brain activity by detecting changes associated with blood flow. Neuroscientists have been analyzing fMRI data to study human brain by mostly focusing on the activities of brain regions. This dissertation proposes, designs and implements full correlation matrix analysis (FCMA) to study whole brain interactions in an unbiased way using a compute cluster within a tractable time. Traditional exhaustive full correlation computations would takes years to complete on a modern computer server. In this dissertation, we propose algorithm optimizations and implementation optimizations to speedup by orders of magnitude. In addition, we optimize the most computationally intensive component of FCMA, the voxel selection, on Intel Xeon Phi coprocessors to finish the whole process in seconds. We also adapt FCMA algorithms to the online fashion and build a real-time fMRI system to analyze the interactions of the whole brain interactively to provide the neurofeedback in real time. For offline analysis, our FCMA toolbox finishes a typical brain interaction study in a few minutes using 48 compute nodes; our real-time fMRI system returns a neurofeedback generated by FCMA under 1 second, and updates the voxel selection and the training model in 3 seconds using 48 compute nodes, which meet the real-time fMRI study requirements. We have used the FCMA toolbox to conduct an initial neuroscience study to show the effectiveness of FCMA. When applying FCMA to a simple fMRI dataset in which subjects viewed blocks of faces or scenes, FCMA identifies category-selective brain regions in terms of correlation in medial prefrontal cortex which cannot be found using traditional activity-based analysis approaches.

1 0

Colloquium Speaker Song-Chun Zhu Monday, Nov 16, 12:30pm
by Nicole E. Wagenblast 16 Nov '15

16 Nov '15

Colloquium Speaker Song-Chun Zhu , UCLA Monday, November 16- 12:30pm Computer Science 105 A Cognitive Architecture for Human-Robot Collaborations Based on Spatial, Temporal and Causal And-Or Graphs In this talk, I will present an ongoing effort for developing autonomous robots that can collaborate with humans in real world scenes and tasks. One objective is to explore a cognitive architecture that can embrace modern progresses in vision, cognition, learning, NLP, and cognitive robot using a unified knowledge representation --- the spatial, temporal and causal ang-or graph (STC-AOG). The STC-AOG is a probabilistic, graphical and compositional model that represents stochastic context sensitive grammars for the hierarchical structures in scenes and objects (spatial), in events and actions (temporal), and in the effects of actions on the scenes (causal). In addition, the representation must also consider the theory of mind, i.e the beliefs and intents of others, for collaborations. I will show a few examples of human robot collaborations. Song-Chun Zhu received a Ph.D. degree from Harvard University in 1996. He is currently a professor of Statistics and Computer Science, and director of the Center for Vision, Learning, Cognition and Autonomy at UCLA. His work in computer vision received a number of honors, including the Marr Prize in 2003 for image parsing, the Marr Prize honorary nominations in 1999 for texture modeling and 2007 for object modeling. As a junior faculty he received the Sloan Fellow in Computer Science, NSF Career Award, and ONR Young Investigator Award in 2001. In 2008 he received the Aggarwal prize from the Intl Association of Pattern Recognition for “contributions to a unified foundation for visual pattern conceptualization, modeling, learning, and inference”. He received the Helmholtz Test-of-time prize at 2013. He is a fellow of the IEEE Computer Society since 2011. He is PI of two consecutive ONR MURI projects on Scene/Event Understanding and Commonsense Reasoning respectively. In recent years, he is also interested in situated dialogues and cognitive robots with the support of DARPA MSEE and SIMPLEX projects.

1 1