- ixp1200 - lists.cs.princeton.edu

Receive error from giga port
by Wong Kim Sing 21 Jun '03

21 Jun '03

Hi, I had this problem of receiving error packet from the giga port, here is how the test go. I had created some packets in the microengine, e.g. move($$dxfer0, 0xfffffff1) move($$dxfer1, 0xfffffff3) move($$dxfer2, 0xfffffff5) move($$dxfer3, 0xfffffff7) move($$dxfer4, 0xfffffff9) move($$dxfer5, 0xfffffffb) move($$dxfer6, 0xfffffffd) move($$dxfer7, 0xffffffff) sdram[write, $$dxfer0, packet_buf_addr, 0, 4], ctx_swap move($$dxfer0, 0xfffffff1) move($$dxfer1, 0xfffffff3) move($$dxfer2, 0xfffffff5) move($$dxfer3, 0xfffffff7) move($$dxfer4, 0xfffffff9) move($$dxfer5, 0xfffffffb) move($$dxfer6, 0xfffffffd) move($$dxfer7, 0xffffffff) sdram[write, $$dxfer0, packet_buf_addr, 4, 4], ctx_swap And I send out this packet to the giga port using the "L3fw8_1.uc" microcode from intel reference design. Result obtained as below: 19:21:03.445227 ff:f0:ff:ff:ff:f1 ff:ff:ff:f1:ff:ff ffff 116: fff2 ffff fff5 ffff fff4 ffff fff5 ffff fff6 ffff fff9 ffff fff8 ffff fff9 ffff fffa ffff fffd ffff fffc ffff fffd ffff fffe ffff fff1 ffff fff0 ffff fff1 ffff fff2 ffff fff5 ffff fff4 ffff fff5 ffff fff6 On the first row and the fifth row, it should be "fff3" and "fff5" respectively, but it become "fff2" and "fff4", there is one bit being modified. And also from 2nd row onward,there is some duplication occur, the 2 words "ffff fff5" has been repeated two time in row 4 and row 6. Is there anyone has this similar problem before or do you have any ideal of solving this, please send a email, thank you. Mike Wong Kim Sing R&D Engineer Institute for Communications Research 20 Science Park Road TeleTech Park #02-34/37 Singapore Science Park II Singapore 117674 Tel: 65 68729030 DID : 65 68709320 Fax: 65 67795441 Email: wongks(a)i2r.a-star.edu.sg Website: http://www.i2r.a-star.edu.sg

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IXP1200 timings.
by Liam.Noonan 19 Jun '03

19 Jun '03

Hi, As part of my research into network processors I am examining the IXP1200. I am trying to obtain information regarding the number of cycles/ length of time it takes the IXP1200 to peform the following tasks. 1, move an mpacket from the a port to rfifo 2, moving mpackets from rfifo to the Microengines, SDRAM 3. Moving mpackets from SDRAM and the Microengine to TFIFO 4. Moving mpackets from TFIFO to an out going port. 5. access times for accessing SRAM. I have reviewed the various literature and publications provided by Intel, but obtaining this information is proving challenging. Any information would be appreciated. Thanks Liam Noonan Dept EC&E University Of Limerick Ireland

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IXA SDK 2.01 with IXP12EB
by C.Liacs 19 Jun '03

19 Jun '03

Hello I'm trying to setup Intel IXA SDK 2.01 to work with IXP12EB evaluation board. Currently I have linux 2.3.99-pre3-rmk3 running on IXP but when I tried to load ue.o from SDK, I got this error: ue.o: unresolved symbol get_virtual_mem_map ue.o: unresolved symbol get_physical_mem_map ue.o: unresolved symbol get_virt_from_phys I found these functions in "mm-ixp1200.h" file in Linux kernel supplied with SDK but I couldn't get this kernel running on ixp12eb. I would appreciate any help. Regards, Charlie

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RE: [ixp1200] Monitoring the IXBus using Workbench
by Botham, Mick 18 Jun '03

18 Jun '03

Liam, The Workbench will show cycles for the microengines and the IX bus, the 'IX bus device status' shows the IX data bus and the status pins, so you can see the cycle count when EOP is asserted, a data watch on the RFIFO elements will show you when the MPKT is written into the RFIFO. I ran the L3fwd8_1f project, this looks like 8 microengine cycles to transfer the MPKT into the RFIFO. Rgds -----Original Message----- From: Liam.Noonan [mailto:Liam.Noonan@ul.ie] Sent: 17 June 2003 12:35 To: 'ixp1200(a)CS.Princeton.EDU' Subject: [ixp1200] Monitoring the IXBus using Workbench Hi, I am trying to determine the amount of cycles/time required to transfer an Mpacket from an IXF 440 to RFIFO. I have loaded and examined the receive code from chapter 5 in the IXP 1200 book. The history window however displays the information from the microengine point of view. I am interested from both the IXF 440 and RBS point of view the amount of cycles each unit utilises to accomplish this task. Any suggestions as to how I can view this information on workbench would be appreciated. Regards Liam University of Limerick Ireland

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Monitoring the IXBus using Workbench
by Liam.Noonan 17 Jun '03

17 Jun '03

Hi, I am trying to determine the amount of cycles/time required to transfer an Mpacket from an IXF 440 to RFIFO. I have loaded and examined the receive code from chapter 5 in the IXP 1200 book. The history window however displays the information from the microengine point of view. I am interested from both the IXF 440 and RBS point of view the amount of cycles each unit utilises to accomplish this task. Any suggestions as to how I can view this information on workbench would be appreciated. Regards Liam University of Limerick Ireland

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FW: [ixp1200] ld DWARF error
by David Mentre 16 Jun '03

16 Jun '03

I repost my message from this morning without the attachement. You'll find the script in the below url. -----Original Message----- From: David Mentre Sent: Monday, June 16, 2003 9:26 AM To: 'ixp1200(a)CS.Princeton.EDU' Subject: RE: [ixp1200] ld DWARF error Hello Cyrus, > From: Cyrus Hall [mailto:hallcp@cs.colorado.edu] > David Mantre's instructions are good, but I need C++ support, so only > recompiling ld seems like the best solution. You're lucky. Jeremy McNicoll also needed C++ support and made a fully automatized script to build the cross toolchain: http://lists.arm.linux.org.uk/pipermail/linux-arm/2003-May/005450.html Best regards, d.

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ld DWARF error
by Cyrus Hall 13 Jun '03

13 Jun '03

I've been moving some C++ code over to the ARM lately and have run into the following error upon linking a particular program with a library I have also ported over: collect2: ld terminated with signal 11 [Segmentation fault], core dumped /usr/local/armbe/armv4b-unknown-linux/bin/ld: Dwarf Error: Could not find abbrev number 66. /usr/local/armbe/armv4b-unknown-linux/bin/ld: Dwarf Error: Invalid or unhandled FORM value: 14. I used the same procedure to compile and link this particular library as several others I've ported over, and the others work just fine and dandy. If I comment out the library calls in the trouble program, every thing compiles fine. I am staticly linking. Goolge makes this appear as a binutils issue. Needless to say, this is rather disheartening, as I don't relish the idea of having to figure out how to upgrade the dev environment. I have read over David Mantre's toolchain howto from some time ago, and that's where I go next unless someone has a save. Anyone one else seen and delt with this issue? Thanks, Cyrus

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Re: [ixp1200] Question on uEngine C compiler
by Shyamal Pandya 13 Jun '03

13 Jun '03

That is because there are a total of 64 sram xfer registers, so each of the four contexts of a microengine gets 16 locally addressable xfer regs, out of which 8 are read and 8 are for write. Maybe you should use global addressing for your xfer registers, which will give you access to more than 8 read xfer registers. Of course will mean you can access fewer local registers. -- Shyamal Pandya Arizona State University Addr: 920 S Terrace Rd #102 Tempe AZ 85281 Phone: 1-480-966-1982 >From: "xtan" <xtan(a)csnet1.cs.tsinghua.edu.cn> >Reply-To: ixp1200(a)CS.Princeton.EDU >To: <ixp1200(a)CS.Princeton.EDU> >Subject: [ixp1200] Question on uEngine C compiler >Date: Fri, 30 May 2003 20:49:31 +0800 > >Hello everybody, >Recently, I encountered a problem that I have to read 16 long words from >SRAM one at a time. But the sram_read intrinsic function can only support >up >to 8 long words. Besides, implementing 16 sram_reg in array format (ex. >X[16]) seems impossible.(Only 8 are allowed) > >Does anyone have good suggestions? Thanks in advance. > >Zhangxi Tan > _________________________________________________________________ Protect your PC - get McAfee.com VirusScan Online http://clinic.mcafee.com/clinic/ibuy/campaign.asp?cid=3963

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Re: [ixp1200] ACE question
by nikhil rao 10 Jun '03

10 Jun '03

This time I am trying to send a packet from the stack ace to the L3 forwarder ace using the following binding in the ixsys.config-l3fwdr bind regular stackace/tx L3Fwdr I have defined the ix_action_default in the L3Fwdr.cpp file. where I simply pass the buffer to the ifaceOutput ace. My expectation is that ix_action_default gets called for every packet that gets sent through the stackAce from the TCP/IP stack. but this doesn't happen. Does anyone have any clue why this could be the case ? Thanks, Nikhil >From: "nikhil rao" <nikhil_p_rao(a)hotmail.com> >Reply-To: ixp1200(a)CS.Princeton.EDU >To: <ixp1200(a)CS.Princeton.EDU> >Subject: [ixp1200] ACE question >Date: Mon, 9 Jun 2003 08:54:36 -0700 > >I need to send a packet from a Linux user application to the core component >of the L3Fwdr >ace. This packet will pass through the stack ace. Right now the stack ace >is >bound to egress >ace. What is the mechanism for hooking the stack ace to some callback >function in the >L3Fwdr ? > >Nikhil _________________________________________________________________ The new MSN 8: advanced junk mail protection and 2 months FREE* http://join.msn.com/?page=features/junkmail

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Re: [ixp1200] ACE question
by Shyamal Pandya 09 Jun '03

09 Jun '03

Hi Nikhil, You can implement a crosscall function in the L3Forwarder microace using the idl provided. Then you can call that function from the stack ace. The SDK Reference and the SDK Guide provides the necessary information on how to implement and invoke crosscall api. -- Shyamal Pandya Arizona State University Addr: 920 S Terrace Rd #102 Tempe AZ 85281 Phone: 1-480-966-1982 >From: "nikhil rao" <nikhil_p_rao(a)hotmail.com> >Reply-To: ixp1200(a)CS.Princeton.EDU >To: <ixp1200(a)CS.Princeton.EDU> >Subject: [ixp1200] ACE question >Date: Mon, 9 Jun 2003 08:54:36 -0700 > >I need to send a packet from a Linux user application to the core component >of the L3Fwdr >ace. This packet will pass through the stack ace. Right now the stack ace >is >bound to egress >ace. What is the mechanism for hooking the stack ace to some callback >function in the >L3Fwdr ? > >Nikhil _________________________________________________________________ STOP MORE SPAM with the new MSN 8 and get 2 months FREE* http://join.msn.com/?page=features/junkmail

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Help reg problem with scheduler-worker design.
by Jagannathan Iyer Venkatesan 09 Jun '03

09 Jun '03

Hi, I have succeded in making the scheduler-worker design work for packets that are less than 214 bytes (size includes all the headers including the MAC header size; with UDP, the size of UDP data is 170 bytes). I have avoided reading stale rcv_rdy_lo flag by looping around using the RCV_RDY_CNT register. But when I increase the packet by 215 byte (in UDP datagram, this translates to 171 bytes of UDP data), I see overflow in the MAC registers. Also, the scenario is peculiar and is explained as follows : I use my UDP client which sends 1) a single 22 byte data first (always) [64 byte packet after MAC layers' encapsulation]. No problem with this packet. /* Also, any packet size above this will make it successfully. */ 2) Send packets of data size 171 bytes repeatedly!! The strange this, every other 171 packet makes it across to the destination. The first one does not cause any MAC overflow but the next one does cause a MAC overflow. The third 171 one makes it across the board. The fourth 171 fails. This goes on. (171 + 44 = 215 after MAC encapsulation. 64 *3 = 192; 64*4 = 256; and so the last chunk has ractional data of size 23 bytes) { the same packet sending can be repeated with data size = 172,173, etc. } 3) If I increase to very large packets, eg 234 butes, the first one and subsequent ones never make it across the board. Between packets, I have a getchar() and on key stroke, I send packets. The machines are in a linear configuration, i.e source <==> IXP <==> destn. The destn does not send any packet back. I think there is no overflow of the RCV_REQ_CNT byte in the RCV_RDY_CNT register because just 4 chunks have come. Can anyone suggest why I am getting this problem ? Any pointers will be very helpful. Jagan. PS : To gain more insight, the design looks almost as the transaltion of the following pseudocode. The thread allocation to the port is static and there is only one thread that takes care of receive from one port. The scheduler is working as follows : while(1) { read_reg(rcv_rdy_lo); old = read( RCV_RDY_CNT); /* reads value as X*/ if(rcv_rdy_lo==0) continue; see_which_microengine_has_to be informed(); construct_the_rcv_req(other_uc_TID); // so that the correct // microengine is signalled write_to_rcv_req(); new=read(RCV_RDY_CNT);/*reads value as X if transfer is not over reads value as X+1 if transfer is over. while(old <=new) { new=read(RCV_RDY_CNT); /* if X+1, then quit. */ } The worker thread looks like : while (1) { wait_for_signal(start_receive); read_the register(rcv_cntl); read_the packet_from_fifo(); eop=process_the packet(); if(eop) { peek intocache and tranmit the packet to the outgoing i/f } else { assemble the packet till eop comes. } }

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PETH driver
by Eng Kean 05 Jun '03

05 Jun '03

Hi, I'm trying to use PETH driver for interplane communication. I'm using non-ACE framework, VxWorks RTOS and IXP1200 Ethernet Evaluation Board. Any documentation explaining how to use PETH driver? Any example codes for data plane and control plane communication using PETH driver, or any other methods? Thanks. Regards, Eng Kean __________________________________ Do you Yahoo!? Yahoo! Calendar - Free online calendar with sync to Outlook(TM). http://calendar.yahoo.com

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[vera] I want to get a start-point
by Cho, joon-woo 04 Jun '03

04 Jun '03

Hello. I got a Vera source code from VERA homepage. Before I start to analyze this source code, can I get a start-point? In other words, is there a implementation document? Plz send me answer. Thanks in advance.

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Embedded Linux, board initialization and loading microengines
by Robert Klima 04 Jun '03

04 Jun '03

Hi together, this question goes to everyone using embedded linux on the enp-2505 which has an ixp1200 and one IXF440 onboard. Hope there are some. ;) I am currently coding an MPLS-Router based on above hardware. To keep it fast and profiling simple I am handling all tasks in the microengines and therefore want to avoid ACEs. When switching from simulation, which worked fine, to hardware debugging I ran into trouble. Though receival of packets worked fine in simulation the code keeps waiting for mpackets when doing hardware debugging. The following loop (from Johnson and Kunze) keeps going forever : do { csr_read((void *)&rcv_ready_bits, rcv_rdy_lo, 1, ctx_swap); } while ( !(rcv_ready_bits & (1 << port_num)) ); The SDK was instructed to "start ports" and IX-Bus-Config is 64Bit, 1-2 MACs. To prepare the Hardware for Debugging I ran bootixp and after that insmod ue.o; insmod octmac.o; rs_udebug; Its definitely no hardware or cabling problem as the supplied l3forwarding_example (./ixstart) works fine. When instead of the above preparations loading an ace-example with (debug mode 1 - Download and debug via workbench) and inserting my own code debugging works as expected. This leads to the following questions : *** Question start here :-) What (else) has to be done to properly initialize the hardware ? Tried some ioctls() on octmac.o but could not find a promising sequence due to a lack of documentation on that subject. To configure a bunch of machines I have been looking for alternative ways to inject the microcode. A program/library that can be used to load+start the microengines would be of great interest. Though some libraries have functions with promising names there are too many and docomentation is to sparse to start guessing. Any suggestions are welcome. Thanks a lot in advance. Yours, Robert. -------------------------------------------------------------------------- Here some information on the Hard-/Software in use : > WARNING: IXF440 MAC Address Initialzation failed. sts = 130 > Press space bar to stop auto-boot... > 0 > Flash download mode is 1 > Cygmon, the Cygnus ROM monitor. > Cygmon was written by Robert Richardson and Bob Manson of Cygnus Solutions > Copyright(c) 1997, 1998, 1999 Cygnus Solutions > > Version: release 2.04 > This image was built on Fri Feb 22 16:35:14 PST 2002 > > CPU: IXP1200 StrongARM(R) Microprocessor rev. C0 > Board: Intel(R) PA1104 Network Processor Base Card > StrongARM is a Registered Trademark of Advanced RISC Machines Limited. > Intel is a Registered Trademark of Intel Corporation > Other Brands and Trademarks are the property of their respective owners. > Waiting for host based download Kernel in use : > Linux ixp_target 2.3.99-pre3-rmk3-np2 #235 Fri Feb 21 13:51:33 CET 2003 armv4b Software: IXA SDK 2.01a IXA Education Workstation (CD from 05/28/2002) -------------------------------------------------------------------------- -- There are three ways to get something done: (1) Do it yourself. (2) Hire someone to do it for you. (3) Forbid your kids to do it.

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xmit_csr details
by Liam.Noonan 03 Jun '03

03 Jun '03

Hi, Where can I find details of the xmit_csr? I have the Intel press book and they cover some of the csr's but not all. Is a csr used when the ME is checking to see if the valid bit is set in the TFIFO entry? Thanks Liam Noonan University of Limerick Ireland

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RE: RE: [ixp1200] l3fwdr
by Botham, Mick 03 Jun '03

03 Jun '03

Vikram You are welcome to try this code (below) I've used it on the IXP1200 dev board, I don't know how much different this is to your board. Rgds Mick /*************************************************************************** *** * * PHY.C * * Access MII and symbol PHYs. * * Revision history : Created March 1997 Updated October 2001 Updated April 2003 * WARRANTY DISCLAIMER. INTEL AND ITS SUPPLIERS MAKE NO WARRANTIES WITH RESPECT TO TECHNOLOGY, EITHER EXPRESS OR IMPLIED, INCLUDING ANY IMPLIED WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE OR ANY IMPLIED WARRANTY OF NONINFRINGEMENT. TECHNOLOGY IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND. LIMITATION OF LIABILITY. INTEL AND ITS SUPPLIERS SHALL NOT BE LIABLE FOR ANY PROPERTY DAMAGE, PERSONAL INJURY, LOSS OF PROFITS, LOSS OR CORRUPTION OF DATA OR USE, INTERRUPTION OF BUSINESS OR ANY SPECIAL, DIRECT, INDIRECT, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY, CONTRACT, STRICT LIABILITY OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE OR LOSS. INTEL AND ITS SUPPLIERS DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS RELATING TO THE TECHNOLOGY PROVIDED. IT IS THE RECIPIENTS OBLIGATION TO BACK-UP OR SAVE ANY STORED DATA. **************************************************************************** **/ #include <stdio.h> typedef unsigned char BYTE; typedef unsigned short WORD; typedef unsigned long DWORD; /* functions' prototypes*/ int PHYread_reg (int port, int phyadd, int reg_offset); int PHYwrite_reg (int port, int phyadd, int reg_offset, unsigned short value); void LED_FLASH (); /* static functions*/ static void PHYgen_tristate (int base_port); static void PHYwrite_mii (int base_port, DWORD mii_data, int size); static int SERCOMread_reg (int port); static void SERCOMwrite_reg (int port, DWORD value); /*-------------------------------------------------------------------------- -- | MII management : | | | | The MII management interface consists of two pins : MDIO and MDC. | | When reading or writing a bit from/to the PHY, its value should be | | read or written to MDIO and MDC should be rotated (once high and once| | low). | | | |--------------------------------------------------------------------------- -- | Accessing MII management through the dec21440: | | | | SER_COM register has 3 relevant bits: | | | | MDM : Mii Data Mode : setting this bit sets the MDIO pin to output mode, | | resetting it sets the pin to input mode. | | MDC : writing this bit sets the MDC pin | | MDIO : writing this bit sets the MDIO pin, reading this bit reads the| | value from the MDIO pin. | | | ---------------------------------------------------------------------------- */ /*========================================================================== ====== = Accessing MII PHY registers : = = The management should write the following frame to the MII PHY : = = +----------------------------------------------------------------+ = | Management frame fields | = +------+-------+----+----+-------+-------+----+------------------+-----+ = | | PRE | ST | OP | PHYAD | REGAD | TA | DATA |IDLE | = +------+-------+----+----+-------+-------+----+------------------+-----+ = |Read | 1...1 | 01 | 10 | AAAAA | RRRRR | Z0 | DDDDDDDDDDDDDDDD | Z | = +------+-------+----+----+-------+-------+----+------------------+-----+ = |Write | 1...1 | 01 | 01 | AAAAA | RRRRR | 10 | DDDDDDDDDDDDDDDD | Z | = +------+-------+----+----+-------+-------+----+------------------+-----+ = = PRE : preamble (32 bits of '1' on MDIO) = ST : Start frame = OP : operation mode (read or write) = PHYADD : Phy address = REGADD : Register's internal address = TA : turnaround - in 'read' operation - tristate on the MII's IO pin, the phy = should write '0' on the next MCLK cycle. = in 'write' operation - write 10 on the IO pin. = DATA : register's contents (16 bits) on MDIO = ============================================================================ ====*/ #define MII_ACS_PREAMBLE 0xFFFFFFFF #define MII_ACS_PREAMBLE_LEN 32 #define MII_ACS_READ_MASK 0x60000000 #define MII_ACS_WRITE_MASK 0x50020000 #define MII_ACS_PHYADD_ALIGN 23 #define MII_ACS_REGADD_ALIGN 18 #define SER_COM (0x8 * 0x4) #define MDM 0x20 #define MDIO 0x10 #define MDC 0x8 #define MDIO_BIT_POSITION 4 #define PASS 0 #define FAIL 0xFFFF /*************************************************************************** ** PHYread_reg This function reads an MII PHY registers. Input parameters: int port - the IXF440 port number int phyadd - the PHY address int reg_offset - the PHY's register offset Output parameters: none Return value: Data from PHY if the reading succeded (the PHY responded), FAIL otherwise. **************************************************************************** / int PHYread_reg (int port, int phyadd, int reg_offset) { int base_port, frame, value, retval, i; BYTE ser_val, dbit; /* write preamble*/ PHYwrite_mii (port, MII_ACS_PREAMBLE, MII_ACS_PREAMBLE_LEN); /* prepare command word*/ frame = phyadd << MII_ACS_PHYADD_ALIGN; frame |= reg_offset << MII_ACS_REGADD_ALIGN; frame |= MII_ACS_READ_MASK; PHYwrite_mii (port, frame, 14); /* tristate*/ PHYgen_tristate (port); /* check that the PHY responded with zero bit*/ ser_val = SERCOMread_reg (port); if ((ser_val & MDIO) != 0) retval = FAIL; /* read data from PHY*/ ser_val &= ~MDM & ~MDC ; /* change to input mode*/ for (i=0; i< 16; i++) { SERCOMwrite_reg (port, ser_val); SERCOMwrite_reg (port, ser_val | MDC); ; dbit = ((BYTE)(SERCOMread_reg (port)) & MDIO) >> MDIO_BIT_POSITION; (value) = ((value) << 1) | dbit; } PHYgen_tristate (base_port); return (value); } /*************************************************************************** ** PHYwrite_reg This function writes an MII PHY register. Input parameters: int port - the IXF440 port number int phyadd - the PHY address int reg_offset - the PHY's register offset unsigned short value - the value to be written to the register. Return value: none. **************************************************************************** / int PHYwrite_reg (int port, int phyadd, int reg_offset, unsigned short value) { int base_port; DWORD frame; /* write preamble */ PHYwrite_mii (port, MII_ACS_PREAMBLE, MII_ACS_PREAMBLE_LEN); /* prepare command word */ frame = phyadd << MII_ACS_PHYADD_ALIGN; frame |= reg_offset << MII_ACS_REGADD_ALIGN; frame |= MII_ACS_WRITE_MASK; PHYwrite_mii (port, frame, 16); /* write data */ PHYwrite_mii (port, (DWORD)value << 16, 16); PHYgen_tristate (port); return(PASS); } /*************************************************************************** ** PHYwrite_mii This function writes a buffer of data to the MII phy. Input parameters: int base_port - the IXF440 port to which we should write SER_COM (port 0 of the chip on which our port is) DWORD mii_data - the data buffer to write to the PHY. The data will be written with MSB first. int size - the size of data (in bits) we wish to write. Return value: none **************************************************************************** / static void PHYwrite_mii (int port, DWORD mii_data, int size) { BYTE dbit, /* data bit */ ser_val; int i,j; ser_val = (BYTE)(SERCOMread_reg (port)) & (~MDC & ~MDIO & MDM); /* leave only the bits not related to PHY access*/ for (i=size; i>0; i--) { dbit = (BYTE)(mii_data >> (31 - MDIO_BIT_POSITION)) & MDIO; SERCOMwrite_reg (port, ser_val | MDM | dbit ); j++; /*slow the loop down*/ SERCOMwrite_reg (port, ser_val | dbit | MDM | MDC); mii_data = mii_data << 1; } } /*************************************************************************** ** PHYgen_tristate This function generates tristate on the phy's MDIO pin. Input parameters: int base_port - the IXF440 port to which we should write SER_COM (port 0 of the chip on which our port is) Return value: PASS if the reading succeded (the PHY responded), FAIL otherwise. **************************************************************************** / #define MII_WRITE_TS 0 static void PHYgen_tristate (int port){ BYTE ser_val; ser_val = (BYTE)(SERCOMread_reg (port)) & (~MDIO & ~MDC & ~MDM); SERCOMwrite_reg (port, ser_val | MII_WRITE_TS); SERCOMwrite_reg (port, ser_val | MII_WRITE_TS | MDC); } /*************************************************************************** ** SERCOMread_reg This function reads data from the MAC ser_com port. Input parameters: int base_port - the IXF440 port to which we should read from SER_COM (port 0 of the chip on which our port is) Return value: data from PHY if the reading succeded (the PHY responded), FAIL otherwise. **************************************************************************** / static int SERCOMread_reg (int base_port) { int *p_SER_COM, value; p_SER_COM=0x38400020; value = *p_SER_COM; return (value); } /*************************************************************************** ** SERCOMwrite_reg This function writes data to the MAC ser_com port. Input parameters: int base_port - the IXF440 port to which we should read from SER_COM (port 0 of the chip on which our port is) Return value: none **************************************************************************** / static void SERCOMwrite_reg (int port, DWORD value) { int *p_SER_COM; p_SER_COM=0x38400020; *p_SER_COM = value; } void LED_FLASH () { int *p_GMII_MNG_ACC; int value; /*turn off the gigabit MDIO,MDC as these lines are shared*/ p_GMII_MNG_ACC=0x038408128; *p_GMII_MNG_ACC=0x0; /*flash the leds on port0 phy*/ PHYwrite_reg(0x0,0x0,0x14,0xBBB2); }

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Question on uEngine C compiler
by xtan 30 May '03

30 May '03

Hello everybody, Recently, I encountered a problem that I have to read 16 long words from SRAM one at a time. But the sram_read intrinsic function can only support up to 8 long words. Besides, implementing 16 sram_reg in array format (ex. X[16]) seems impossible.(Only 8 are allowed) Does anyone have good suggestions? Thanks in advance. Zhangxi Tan

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Ethernet to Giga port packet forwarding
by skdas＠i2r.a-star.edu.sg 29 May '03

29 May '03

Hi, I'm a bignner in this area. My task is to send/receive packet from/to Ethernet to/from Giga port using microcode. Anyone have the source code for this, else any suggestions are welcome. With thanks and regards, Santos I2R, Singapore

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Installing problems
by Alejandro Moreno 27 May '03

27 May '03

We have problems installing the enp-2505 board. We followed IXA Education Workstation Setup Guide step by step. The problem is in section 7 (Booting ENP-2505 board), after execute the manual boot in linux terminal, there is no response... we check pc serial communication and it is good, but the enp-2505 board doesn't have serial communication. It is important to say that our pc has different characteristics of the one mentioned in the guide: - We don't have Dell Precision WS, our pc is generic (Pentium4 on intel motherboard). - WinXP (no problem with vmware in linux, is it important that pc most have Win2000?). - One hard disk (no booting problems). best regards!

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RE: [ixp1200] using addresses of labels
by Arthur Berkovitch 27 May '03

27 May '03

Hi Cyrus, Use the JUMP instruction: jump[register, label#], targets [label1, label2, ...labeln], optional_token Also, you may find the .func_table directive useful for your needs. If wanted, you can export the labels addresses to core applications with the .export_func directive. take care, Arthur -----Original Message----- From: Cyrus Hall [mailto:hallcp@cs.colorado.edu] Sent: Wednesday, May 14, 2003 1:28 AM To: ixp1200 List Subject: [ixp1200] using addresses of labels Hi there all- I'm currently trying to build a table of address to parts of a filter I've written. IE, you have a value, index into the table, and jump to the associated address in code. The jumping is simple enough, save the PC and replace it, give up control, and wait for the ctx switch back in. Not hyper efficient, but not bad when you're only filter one or two fields. Returning is simple enough as well. The problem I'm having is actually get the address of code. This clearly needs to be done at compile time (there doesn't appear to be a linker involved in loading code onto the ME's), and would seem to be as simple as replacing the symbolic label with it's final address. Yet, there seems to be no way to do something like: immed32[var, label#:] Has anyone done anything like this and\or know how? Thanks, Cyrus

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IXP2400/Linux routing sample
by Mirko Benz 26 May '03

26 May '03

Hello, We are using an IXDP2400 with a Gigabit module. So far we managed to set up a cross compiler, get Linux running and explored small sample programs on the hardware. Unfortunately the Linux support of the SDK is still incomplete. We are facing problems with the Linux Gigabit interface driver (does not find the board during boot up). On the other hand, the initialization part for the routing application is for VxWorks only... Has anyone managed to get the routing application running? Help/comments are very much appreciated. Regards, Mirko

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Re: [ixp1200] IXP1200 timings.
by Shyamal Pandya 23 May '03

23 May '03

The FBI units cycle counter can be read from the microengines using the csr instruction.. I have used the instruction. The paper mentions "instrumenting the code to use the IXP1200 cycle counter" Is that what you mean by that, or are you doing anything else? -- Shyamal Pandya Arizona State University Addr: 920 S Terrace Rd #102 Tempe AZ 85281 Phone: 1-480-966-1982 >From: "Yitzchak M. Gottlieb" <zuki(a)CS.Princeton.EDU> >Reply-To: ixp1200(a)CS.Princeton.EDU >To: "'ixp1200(a)CS.Princeton.EDU'" <ixp1200(a)CS.Princeton.EDU> >Subject: Re: [ixp1200] IXP1200 timings. >Date: Fri, 23 May 2003 10:19:36 -0400 (EDT) > >On Fri, 23 May 2003, Liam.Noonan wrote: > > > I am trying to obtain information regarding the number of cycles/ length >of > > time it takes the IXP1200 to peform the following tasks. > > > > 1, move an mpacket from the a port to rfifo > > 2, moving mpackets from rfifo to the Microengines, SDRAM > > 3. Moving mpackets from SDRAM and the Microengine to TFIFO > > 4. Moving mpackets from TFIFO to an out going port. > > 5. access times for accessing SRAM. > > > >There is a Princeton University technical report, >http://www.cs.princeton.edu/nsg/papers/ixp.html, and an SOSP paper >http://www.cs.princeton.edu/nsg/papers/ixp-sosp.html by Tammo Spalink that >addresses at least some of these questions. > >Zuki > >-- >Yitzchak Gottlieb >zuki(a)CS.Princeton.EDU > > _________________________________________________________________ Help STOP SPAM with the new MSN 8 and get 2 months FREE* http://join.msn.com/?page=features/junkmail

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Question on setup ENP2505, urgent!
by feng 22 May '03

22 May '03

Hello, I got a ENP2505 board from my supervisor. He joined the intel IXA university program. But when I tried to setup this board according to the IXA Education Workstation Setup Guide, I always failed in Section 7. After I finished install software for ENP2505 and tried to boot the board using " ./bootixp " boot script, the board always entered a Cygmon environment and also I can not see the message "Finished ENP-2505 driver install" as mentioned in this guide. Then I tried to ping the board in another terminal window, it failed. I thought it's true. Because actually the Linux system do unknow the board currently. So, is there anybody know which options I should choose before I boot the enp2505 board. VxWorks, System Monitor or Cygnmon mode in this step? Do u know what's the problem? best, feng

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Hack to boot Linux on IXP2400
by David Mentre 22 May '03

22 May '03

Hello, I have documented the hack that allows to boot Deepak Saxena Linux kernel on IXP2400 with an old RedBoot. As usual, you'll find in at: http://www.linux-france.org/~dmentre/doc/en/ As pointed out several times by Deepak, this is a *hack* that is not intended to work in the future. Hope it will help others, ;-) Best regards, d. -- David Mentré <mentre(a)tcl.ite.mee.com> - Research engineer Mitsubishi Electric ITE-TCL / European Telecommunication Research Laboratory Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 http://www.mitsubishi-electric-itce.fr

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Open source network stack?
by Øyvind Hvamstad 21 May '03

21 May '03

Hi, I wonder if there is an open source implementation of a network stack, or a field stack for ENP-2505? I'm not quite sure what a field stack is, but someone told me that a network stack would probably be exceeding the cards resources. Any hint or help is welcome -- Øyvind Hvamstad

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