- ixp1200 - lists.cs.princeton.edu

Re: [ixp1200] (no subject)
by Rayashish＠aol.com 03 Mar '02

03 Mar '02

In a message dated 3/2/02 11:57:20 AM Pacific Standard Time, abhijeet(a)cs.utah.edu writes: I am trying to setup the development environment for IXP 1200 EE board. I 've gone through the document, which says: There are two software development environments designed specifically for IXA application developers. 1. The IXA SDK to develop IXA applications and to write code modules targeted for the IXDP1200 Advanced Development Platform. The IXA SDK runs on Red Hat Linux * 6.2 or Cygwin * (under Windows NT * ) and is available on the IXA SDK distribution CD 1. 2. The IXP1200 Microengine Development Environment to write microcode modules (including those for microACEs) targeted for microengines on the IXP1200. The IXP1200 Microengine Development Environment runsWindows NT-4 I want to know if i can use RHL 7.2 for IXA SDK and Windows 2000 Pro for IXP1200 Microengine Development Environmen. Is it necessary to stick with RHL 6.2 and WinNT-4? Regards, Ashish

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where to get IXP evaluation board ?
by Kostas G. Anagnostakis 02 Mar '02

02 Mar '02

Hi all, Apologies if the question is inappropriate for this list. We have been trying to find a distributor willing to sell us a single evaluation board to us, through the list available on the Intel Web site, but without any success so far. Intel customer service could only point to that list, so that didn't help either. Does any of the university users on this list have any hints to give us on this ? thanks, --kostas

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Just thinking about you. kvb
by yajiliz 02 Mar '02

02 Mar '02

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(no subject)
by Rayashish＠aol.com 02 Mar '02

02 Mar '02

Hi all, The minimum requirements for IXP SDK2 are NT-4 and Linux-6.2. Is OK to use windows 2000 pro. and Linux-7.2. Regards, Ashish

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RE: [ixp1200] (no subject)
by Ranjeeta 01 Mar '02

01 Mar '02

Hi, Which version of SDK is it? Is it SDK 2.0 or SDK 2.01? -Ranjeeta -----Original Message----- From: Abhijeet Joglekar [mailto:abhijeet@cs.utah.edu] Sent: Friday, March 01, 2002 7:27 PM To: ixp1200(a)CS.Princeton.EDU Subject: Re: [ixp1200] (no subject) I am working with the Bridalveil card and I have installed the PCI drivers and the SDK on Linux 7.2. As for windows, I think the drivers to communicate might not work with ME and other versions, between NT and 2000, I am not sure. But if you are using just the commandline assembler on Windows, then it doesnt make difference which Windows version you install on. -abhijeet On Fri, 1 Mar 2002 Rayashish(a)aol.com wrote: > Hi all, > The minimum requirements for IXP SDK2 are NT-4 and Linux-6.2. > Is OK to use windows 2000 pro. and Linux-7.2. > Regards, > Ashish >

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RE: [ixp1200] doorbell interrupt?
by Preston, Charles E 01 Mar '02

01 Mar '02

Mirko, The only PCI function available from the uEngine is the DMA function. Doorbell registers are not accessible from the uEngines. If you want to generate an interrupt to the StrongARM, you can use IREG. That's the only source of interrupts from the uEngine to the control plan. Regards, Carlo -----Original Message----- From: Mirko Benz [mailto:benz@mephisto.inf.tu-dresden.de] Sent: Friday, March 01, 2002 8:47 AM To: ixp1200(a)CS.Princeton.EDU Subject: [ixp1200] doorbell interrupt? Hi, Is it possible to write to the doorbell register from uEngines? Or are there other opportunities to generate interrupts from there? Regards, Mirko

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RE: [ixp1200] Query regarding NCL
by Preston, Charles E 01 Mar '02

01 Mar '02

Ashley, NCL runs only on the StrongARM. All of the classification at the microengine level would be done within microblocks. Regards, Carlo -----Original Message----- From: Ashley Thomas [mailto:athomas@unity.ncsu.edu] Sent: Thursday, February 28, 2002 11:35 PM To: ixp1200(a)CS.Princeton.EDU; ixp(a)cc.gatech.edu Subject: [ixp1200] Query regarding NCL hi all, The NCL that we use in ACE to classify the packets: does that run at the StrongArm ? or can it run on StrongArm as well as the uE ?? Any pointers is appreciated.. thanks Ashley

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doorbell interrupt?
by Mirko Benz 01 Mar '02

01 Mar '02

Hi, Is it possible to write to the doorbell register from uEngines? Or are there other opportunities to generate interrupts from there? Regards, Mirko

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Query regarding NCL
by Ashley Thomas 01 Mar '02

01 Mar '02

hi all, The NCL that we use in ACE to classify the packets: does that run at the StrongArm ? or can it run on StrongArm as well as the uE ?? Any pointers is appreciated.. thanks Ashley

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flashing amber led
by John H. Hartman 28 Feb '02

28 Feb '02

Probably a stupid question, but what does a flashing amber led on the 10/100 ports mean? -- John

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Date: Thu, 28 Feb 2002 11:25:30 -0800
by Yavatkar, Raj 28 Feb '02

28 Feb '02

Hi All: Here is a great new book that explains how to program 1200 with useful caveats and lots of good examples (comes with a CD containing working code) Amazon: http://www.amazon.com/exec/obidos/ASIN/097128878X/qid=1014917482/sr=8-1/ref= sr_8_1_1/102-9277335-3925739 Fatbrain: http://www1.fatbrain.com/asp/bookinfo/bookinfo.asp?theisbn=097128878X&vm= Barnes and Noble: http://shop.barnesandnoble.com/booksearch/isbnInquiry.asp?userid=22QBB1PCHO& mscssid=SFFP3NQR0UD69H7XX96JME39C5MPBKS7&isbn=097128878X

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Vera build problem
by John H. Hartman 25 Feb '02

25 Feb '02

In trying to build IPmm and linking with libixprouter.a I'm getting memRead16 and memWrite16 as undefined. They are used in pktgen.c. Should they changed to memRead16be and memWrite16be, which are defined? -- John

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Does anyone know how to enable ip_forwarding function of BV Linux?
by Victor 21 Feb '02

21 Feb '02

Hi, all I'm testing some program on SDK2.0, which has Linux running on StrongARM(the kernel version is 2.3.99-pre3-rmk3-np2). I wonder how to enable ip_forwarding on that version. It was said that you can use "echo 1 > /proc/sys/net/ipv4/ip_forwarding" to enable it on recent version, but I can't find that file on StrongARM. Thanks Victor

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SDK 2 Linux, ...
by Mirko Benz 21 Feb '02

21 Feb '02

Hi, new to the list so some more questions: Is there support for the SDK 2.0 version of Linux for IXP12EB? Are there any updates/patches beyond the 2.3.99 (e.g. 2.4.x) kernel available? The PCI performance figures from the vera paper are not what I would expect. Is this really the maximum or what can be tweaked? Would using the I2O unit help? Are there other (non-INTEL) IXP related resources on the net? Regards, Mirko University of Technology Dresden, Germany

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Microengine C compiler and Micro-ACE programming framework
by Didier CONTIS 20 Feb '02

20 Feb '02

I am trying to look for more info on how to write some Microengine C code that will integrate in the ACE framework. Has anyone look already into this ? Thanks in advance for any reply, Regards - Didier

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Re:Evaluation of Vera
by Tan Chee Wei 01 Feb '02

01 Feb '02

Hi Scott and Zuki, Thank You for the prompt reply. The sgo problem has been resolved now. But may I know under what circumstances does one use "pcireset" ? This program hangs my machine too. I still could not figure out the problem with ping. 192.168.133.38--->[Port 1]Vera[Port 0]--->192.168.133.147 My routing cache is as follows: /* original */ {"192.168.133.38", "192.168.133.147", "00:E0:29:00:8A:57", "00:E0:29:00:8C:AE", 0x00}, {"192.168.133.147", "192.168.133.38", "00:E0:29:00:8C:AE", "00:E0:29:00:8A:57", 0x01}, /*mirror*/ {"192.168.133.38", "192.168.133.147", "00:E0:29:00:8A:57", "00:E0:29:00:8C:AE", 0x01}, {"192.168.133.147", "192.168.133.38", "00:E0:29:00:8C:AE", "00:E0:29:00:8A:57", 0x00}, Could I confirm that the last parameter ie. "0x00 or 0x01" points to the port that the microengines is supposed to transmit out ? a) The ETHsrc and ETHdst entries in the cache refer to the addresses to be put on the packet. If the ETHdst address does not match the computer to receive the packet the ping might not be recorded. I am still stuck at the point where the microengines can only receive. For each packet received, the SA repeatedly reads and writes as pointed out. None of the packet is transmitted. b) There might not be any microengines servicing the ports. What are the XMT_UE_BASE, XMT_CTX values in Libixprouter/common/src/config.h First, I used the original values: #define RCV_BASE_UE 0 #define RCV_UE_COUNT 2 #define RCV_CTX_COUNT 8 #define XMT_BASE_UE 4 #define XMT_UE_COUNT 2 #define XMT_CTX_COUNT 8 Control_BootUEs gives tid 16, pid 1, ntid 20 tid 20, pid 2, ntid 17 tid 17, pid 3, ntid 21 tid 21, pid 4, ntid 18 tid 18, pid 5, ntid 22 tid 22, pid 6, ntid 19 tid 19, pid 7, ntid 23 tid 23, pid 0, ntid 16 tid 0, pid 1, ntid 4 tid 4, pid 2, ntid 1 tid 1, pid 3, ntid 5 tid 5, pid 4, ntid 2 tid 2, pid 5, ntid 6 tid 6, pid 6, ntid 3 tid 3, pid 7, ntid 7 tid 7, pid 0, ntid 0 Does that mean uengine 0 to 1 are activated for receive and uengine 4 and 5 are activated for transmit ? Now if I change it as such and recompile everything: #define RCV_BASE_UE 0 #define RCV_UE_COUNT 4 #define RCV_CTX_COUNT 16 #define XMT_BASE_UE 4 #define XMT_UE_COUNT 2 #define XMT_CTX_COUNT 8 It means uengine 0 to 3 are utilised for receive and the remaining for transmit ? But the Control_BootUEs remains the same as above. c)I turned on Debugging and recompiled the ue source. But I did not get any new message other than the SA's messages on the minicom console. Am I missing something ? 4)I am interested in the layout of the queue in the memory and how this layout is mapped to the 8 ports. #define QUEUE_NO_BITS 3 #define XMT_Q_COUNT (1 << QUEUE_NO_BITS) This means I have 8 queues per port ? Thank You once again and kind regards, cheewei

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Evaluation of Vera
by Tan Chee Wei 31 Jan '02

31 Jan '02

Hallo, There are a couple of problems and questions which I have while evaluating Vera's software and reading the Princeton papers. I appreciate advice. 1)I tested the software sgo on several machines. One persistent problem is that "sgo X.srec" could only execute once. The subsequent execution would lead to segmentation fault of sgo and the machine would normally freeze. If "sgo X.srec" is used, I got the following errors: +++runIXP1200:signal=0xffffffff expecting entry address(0xC1002000) +++IXP1200 is not a mem target on pri PCI and ...not a bus master on pri PCI. If "sgo -r X.srec" is used, more errors pop up: +++Unable to handle kernel NULL pointer dereference at virtual address 00000000 +++printing eip:00000000 +++*pde:00000000 +++Oops:00000000 +++CPU:0 +++EIP:0010:{<00000000>} +++Eflags:00010097 +++eax ffffe0c ebx:00027396 ecx:c02bb54e0 edx:0x1d +++esi:d1bfc960 edi:0x5622 ebp:c5479b38 esp:c5479b10 +++Process sgo (pid:1497, stackpage=c5479000) +++Call Trace.... +++Bad EIP +++hda:lost interrupt I tried resetting the board first, like using the minicom reset as well as the reset pins on the ixp before repeating the above commands. But I still have the same segmentation fault and bad EIP problem. 2)How does one create the vth0,.... device interface on Pentium as described in the paper ? Will the forwarder's admission control that runs on Pentium be included in future release ? 3)Say, I have a simple receiver and sender set-up 10.60.0.38--->[Port 1]Vera[Port 0]--->192.168.133.147 My routing cache's content is : {"10.60.0.38", "192.168.133.147", "00:80:C7:F6:3A:BB", "00:E0:29:00:8C:AE",0x00} "192.168.133.147", "10.60.0.38", "00:E0:29:00:8C:AE", "00:80:C7:F6:3A:BB",0x01} It seems that my ping packets got forwarded but the acknowledgement did not come back. Then, I used a traffic generator and it could be observed that IP packets get forwarded by IXP1200 as normal but did not get transmitted out of the port. The uengines were polling the sa queue. For each packet, they did the ipmm_packet_read:Reading 64 (out of 64) bytes...at say address 0x00284400 and ended with ipmm_packet_write to the same address 0x00284400. Also, packets could only be transmitted out at port 0 using the command keys at the minicom but not port 1. how could I make my ping work ? 4) Each port has 16 queues. How are they organized ? ie. starting from which address ? Thank You very much and kind regards, cheewei

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MPLS implementation on VERA...
by Qiu Qiang 29 Jan '02

29 Jan '02

Dear All, Currently we are trying to build a router with MPLS integrated using ixp1200 network processor. We would like to enhance the currentVera software with MPLS implementation. Suggestion will be appreciated on the following several issues: 1.) How to implement/load a MPLS forwarder 2.) How to implement a efficient MPLS labeling method 3.) How/Where to insert the MPLS header to packet 4.) What is the best way to balance the work among the three processor hierarchy. Any other issues on MPLS implementation on VERA are welcome to be raised. By the way, is there any existing VERA work on MPLS ? Best Regards, Qiu Qiang

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RE: [ixp1200] Re: Some queries on VERA and the IXP1200EB in gener al.
by Tan Chee Wei 25 Jan '02

25 Jan '02

Dear Poh Kit, >What's the difference between setting up the system with libixprouter >and VERA and plugging it into the PCI slot of a motherboard with a host >processor and just flashing the boot ROM with Cygmon and booting a Linux >kernel image on the original Intel chassis as shown at >http://www.netwinder.org/~urnaik/ixp1200_howto.html ? The main difference is that Princeton's Vera allows a programmer to have more computing power at his disposal if said, one is using the PC+SA+UE configuration. Note that Vera, being a multi-processors design, does not restrict itself to PC+SA+UE configuration. In the IXP1200 hardware reference manual Pg.31,2.7.1, Intel suggests that the SA core may be used in different ways, depending on the application. If the system contains a higher end processor like Pentium, SA can leave system maintenance to Pentium and runs a mini-kernel whilst the Pentium and IXP1200 communicate via PCI bus. Vera accomplishes exactly that. In design where no host processor like Pentium is available such as that described in netwinder, SA is seen as the main processor and runs an RTOS. Vera's router infrastructure and the router in Intel reference designs use different data structures. In short, we have 2 different routers using the IXP1200 board. >Also, are there any archives of the IXP1200 mailing list which I can go >through. This would give me a clearer view of the picture much faster >and maybe avoid asking questions which may have already been asked before.:) do "index ixp1200" to retrieve the archive. do "get ixp1200 filename" to get the specified file in the archive. kind regards, cheewei

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Re: Some queries on VERA and the IXP1200EB in general.
by Scott C. Karlin 24 Jan '02

24 Jan '02

On Thu, Jan 24, 2002 at 12:12:41PM +0800, Chong Poh Kit wrote: > > ... I have some > questions regarding the VERA software from Princeton and also the > IXP12EB (revision B) in general... > > The IXP12EB (Rev. B) that was supplied by Intel currently boots > either VxWorks or Angel/UCOS. Currently, we're booting the hardware > with the VxWorks_Gig binary image found in the IXP SDK 1.3. My > university does not have the Tornado IDE for VxWorks or the VxWorks > RTOS itself. Are these software absolutely necessary for me if I'm > using the VxWorks OS? Yes, I believe so. > If I use the libixprouter package with the VERA software on the > IX12EB, would that be like substituting VxWorks and Tornado with > Linux and VERA? Yes. > What's the difference between developing microcodes for the > stand-alone IXP12EB with the original Intel VxWorks image and the > IX12EB with VERA? Because the StrongARM would be running libixprouter, the interface between the microengines and the StrongARM will be different. > Will it work with microcodes compiled on the IXP SDK ver. 2.0 Linux > Edition? In general, no. I think an analogy would be writing x86 assembly language for Windows and for Linux. The code runs on the same processor and some subroutines would port with no changes; however, code which interfaces with the OS (the StrongARM) would have to change. > I hope you can help answer some of my questions or direct me to > some resources which maybe of some help. The ixp1200 mailing list is a good place to start for ixp1200/VERA questions. Scott

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Using Intel's microcode assembler on Linux
by Yitzchak M. Gottlieb 23 Jan '02

23 Jan '02

It seems that Intel's microcode assembler (v 1.2.76) for the IXP1200 runs under WINE, a Windows compatability layer for Linux. This allows the entire VERA/Libixprouter toolchains to run under Linux. See http://www.winehq.com/ for more information about WINE. Once you have WINE running you can make the following changes in the Libixprouter/ue/src/Makefile: Replace line 43: < AS = $(TOOLSDIR)/uca with: > AS = > # Uncomment the following line to compile under WINE > AS += wine -- > AS += $(TOOLSDIR)/uca This change will be in the upcoming release of Libixprouter which should be available fairly soon. Zuki -- Yitzchak Gottlieb zuki(a)CS.Princeton.EDU

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[ixp1200]subscription
by Jin W. Lee 22 Jan '02

22 Jan '02

subscribe ixp1200

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SRAM Memory Lookup
by S Murali 21 Jan '02

21 Jan '02

Hello, I would like to know how many CYCLES a microengine takes to do a single SRAM memory lookup ? Is it a constant or does it depend on anything ? How does it differ from SDRAM ? Thanks, -Murali

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IXF1002 network statistic registers
by john_zhou＠nai.com 21 Jan '02

21 Jan '02

Hi, Does anyone know how to write program to access to the control registers and network statistic registers of IXF1002 in a intel ixp1200 evaluation board? I noticed there is a directory ixp1200\SA1_CoreLibs\GigaMac_GC82547EB in my installed IXP1200 SDK 2.0, and there should be some APIs there to deal with the IXF1002 registers' accessing. But after I read the source code, I still haven't found any real code to read or write IXF1002's registers. Thanks John

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RE: [ixp1200] SRAM Memory Lookup
by Kalkunte, Suresh S 21 Jan '02

21 Jan '02

Murali, How many microengines contend, how often and what kind of memory accesses (ordered/optimized etc. SRAM/SDRAM) will determine the latencies. To get a ball-park idea of how latencies are affected by the application being executed on the IXP1200, the link to this paper among others might give you some answers <http://www.cs.princeton.edu/nsg/papers/ixp-sosp.html> Suresh -----Original Message----- From: S Murali [mailto:tulasi@csa.iisc.ernet.in] Sent: Sunday, January 20, 2002 11:46 AM To: ixp1200(a)CS.Princeton.EDU Subject: [ixp1200] SRAM Memory Lookup Hello, I would like to know how many CYCLES a microengine takes to do a single SRAM memory lookup ? Is it a constant or does it depend on anything ? How does it differ from SDRAM ? Thanks, -Murali

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