- ixp1200 - lists.cs.princeton.edu

Re: Doubt reg. sending data streams to IXP1200 ports
by sharmila radhakrishnan 07 Apr '04

07 Apr '04

Hello Win an evening with the Indian cricket captain: Yahoo! India Promos.

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Deep packet inspection using IXP1200 simulator
by Denis Lyons 05 Apr '04

05 Apr '04

> Hi, > > I am a masters student who is just starting work with the IXP1200 > simulator. > I am interested in performing deep packet inspection using the simulator > and > analysing the perfromance. Is there any code available for implementing > deep packet inspection on the IXP1200 simulator?? > > Any help or advice will be greatly appreciated. > > Cheers, > > Denis.

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RE: [ixp1200] Transmitting pkts out of Giga ports
by Kunze, Aaron 02 Apr '04

02 Apr '04

Chompi, I think I can answer some of these questions for you. I believe your intuition is correct and the transmit code is not filling the MAC buffers fast enough. The transmit code for this chapter was not tested on the gigabit ports, so it's no surprise that the code is not fast enough. However, the IXF1002 has a 2048 byte buffer per port. So, you should be able to send Ethernet packets of that size or less without underflowing. The trick is to set the "tx send threshold" to something large. This threshold is the number of bytes that must be in the buffer before the MAC starts transmitting. If this threshold is set large enough, you should never underflow. This setting can be adjusted in the simulator, and it can also be adjusted on the hardware using the IXF1002 driver. If you are on Linux, this is done from user space via IOCTLs. If you are on VxWorks, this is done through function calls. There are also two known bugs in the transmit code that we are trying to put up on the errata web page. This may be impacting your ability to run the code on the hardware. I have pasted the errata below. It should be up on the website soon. For your last question, unfortunately, I couldn't find any microC code for transmitting on gigabit ports, but that doesn't mean it doesn't exist. Maybe someone else on the list has something like that. Aaron Errata: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Page: N/A Location: CD-ROM, Chapter09\transmit.c Description: The transmit code supplied in Chapter 9 does not properly handle packets larger than 64 bytes. There are two corrections: First, lines 169 and 170 should read: port_state.current_data_ptr = (void*)((unsigned int)(port_state.current_data_ptr) + (64 / sizeof(long long))); instead of: port_state.current_data_ptr = (void*)((unsigned int)(port_state.current_data_ptr) + 64); This correction accounts for the quad-word addressing of SDRAM on the IXP1200. The second correction is to add the following line after line 167: mpacket->eop = 0; This ensures the the per-mpacket state maintained by the fill threads gets properly initialized for each new packet. ------------------------------ Aaron Kunze Intel Research and Development aaron.kunze(a)intel.com ----PGP Key ID: 0x81124B7C---- ----NOT SPEAKING FOR INTEL---- ---------GO BOILERS!!--------- > -----Original Message----- > From: ixp1200-bounces(a)lists.cs.princeton.edu > [mailto:ixp1200-bounces@lists.cs.princeton.edu] On Behalf Of > chompi(a)softhome.net > Sent: Tuesday, March 30, 2004 4:04 AM > To: ixp1200(a)lists.cs.princeton.edu > Subject: [ixp1200] Transmitting pkts out of Giga ports > > > > Hi all, > > I've recently tried sample code from chap9 Johnson and Kunze > book and in > DWB, the code works fine with Fast Eth ports. However, if I > try to use GE > ports, it only works when MTU<=192 (<=3 Mpkts per pkt). If > there are >3 > Mpkts/pkt, the simulation halts with error "Transmit buffer > underflow". Does > this mean that the code is not filling up TFIFO fast enough? > Anyways, even if I set MTU<=192, I still cannot send out any > traffic on real > hardware (we are using ENP-2506). L3Fwdr reference design > works fine on the > board so I do not expect any hardware or configuration problems. > Did anybody encounter this issue before? Is there any sample > code (in micro > C) lying around that transmits data over GE ports? > > Any help is appreciated. > > Chompi. > _______________________________________________ > ixp1200 mailing list > ixp1200(a)lists.cs.princeton.edu > https://lists.cs.princeton.edu/mailman/listinfo/ixp1200 >

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ixp425 - AccessLibrary1.4 - ATM-Transfer
by Manfred Bergmann 30 Mar '04

30 Mar '04

Hi all, I've got a question concerning the UTOPIA/ATM transfer with the Intel AccessLibrary v1.4 on Linux. I am replenishing with IX_MBUFs that have the size of a page (4k). Access Library fills only 4080 bytes since this is a multiple of 48 bytes payload in AAL0_48 mode. Is there any chance that I get all bytes of a page filled since these pages are user-virtual mem mappings and I don't want to touch the received packets? I need the received data with no interruptions. Any ideas would be very welcome. Regards, Manfred Bergmann

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Transmitting pkts out of Giga ports
by chompi＠softhome.net 30 Mar '04

30 Mar '04

Hi all, I've recently tried sample code from chap9 Johnson and Kunze book and in DWB, the code works fine with Fast Eth ports. However, if I try to use GE ports, it only works when MTU<=192 (<=3 Mpkts per pkt). If there are >3 Mpkts/pkt, the simulation halts with error "Transmit buffer underflow". Does this mean that the code is not filling up TFIFO fast enough? Anyways, even if I set MTU<=192, I still cannot send out any traffic on real hardware (we are using ENP-2506). L3Fwdr reference design works fine on the board so I do not expect any hardware or configuration problems. Did anybody encounter this issue before? Is there any sample code (in micro C) lying around that transmits data over GE ports? Any help is appreciated. Chompi.

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Tornado 2.0 does not display value entered by user
by EK Lee 26 Mar '04

26 Mar '04

Hi all, I am writing a program to get some value from user via tornado 2.0 shell console. The value is received by scanf. But, I found that the value entered by users could not be displayed on the console. However, the value received by the program is correct. Any suggestion how can I make the value visible on the console screen? Thanks. Regards, ek _________________________________________________________________ Using a handphone prepaid card? Reload your credit online! http://www.msn.com.my/reloadredir/default.asp

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Binary format of ME instructions
by Luo, Yan 17 Mar '04

17 Mar '04

Hello, I wonder how to obtain the document on the binary format of ME instructions. In the *.list file, there is a hex value associated with each ME instruction, is the number the binary format of the corresponding instruction? If so, how do I interprete it? Thanks, Yan

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[Announce]: kernel module to reset IXP2400 from host
by romit dasgupta 16 Mar '04

16 Mar '04

Hello all, Many a times while developing kernel modules, I tend to hang my ENP-2611 radisys board. I thought it would be nice to develop an utility to reset the board from my host system. Attached is the source code for the same. It is easy to use. Once you have installed the kernel module in your host system, you can just issue echo "" > /proc/ntb and you can see the ENP board rebooting. The caveats are on the beginning of the source code. I hope it will make life easier for kernel programmers using radisys board. Regards, -Romit /* * This software may be used and distributed according to the terms * of GNU General Public License, incorporated herein by reference. */ /* * Author Romit Dasgupta (romit(a)myrealbox.com) * Apropos Infotech Ltd. (www.aproposinfotech.com), * Future Systems, Inc. (www.future.co.kr). */ /* * 21555 non transparent bridge driver to reset ENP-2611 * board from the host CPU. * After installing this module, if you want to reset * ENP-2611 board, just type * echo "" > /proc/ntb * Caveat: Load this module before invoking a reset * on ENP-2611 from redboot. * This has been compiled for 2.4.20-8 * * Version history : Released on 16th March 2004. * */ #include <linux/module.h> /* module_init, module_exit */ #include <linux/init.h> /* various macros */ #include <linux/pci.h> /* pci related fns */ #include <linux/proc_fs.h> /* proc related */ #include <linux/ioport.h> /* request_mem_region etc. */ #include <asm/io.h> /* ioremap, iounmap */ #ifdef DEBUG #define Debug(message) printk message #else #define Debug(message) #endif #ifndef PCI_DEVICE_ID_INTEL_21555 #define PCI_DEVICE_ID_INTEL_21555 0xb555 #endif #define DOWNSTREAM_XLAT1 0x98 #define CFG_ADDR_UCA_21555 0x88 static volatile char config_space[64*4]; static volatile char *cap_csr; static struct pci_device_id bridge_tbl[] __devinitdata = { {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_21555, PCI_ANY_ID, PCI_ANY_ID, }, {0,} }; static struct pci_dev *pcidev_21555; /* * Got the idea of interface checking from the mvnet source code. */ static int check_21555_interface(struct pci_dev *pdev) { u32 readword = 0, readback = 0; int result; /* * The upstream configuration address register can't be written * from the primary interface. Try to modify this register to * determine which interface we are connected to. */ result = pci_read_config_dword(pdev, CFG_ADDR_UCA_21555, &readword); if (result != PCIBIOS_SUCCESSFUL) { Debug(("21555: Error reading PCI configuration\n")); return -EIO; } result = pci_write_config_dword(pdev, CFG_ADDR_UCA_21555, ~readword); if (result != PCIBIOS_SUCCESSFUL) { Debug(("21555: Error writing PCI configuration\n")); return -EIO; } result = pci_read_config_dword(pdev, CFG_ADDR_UCA_21555, &readback); if (result != PCIBIOS_SUCCESSFUL) { Debug(("21555: Error reading back PCI configuration\n")); return -EIO; } /* Return 1 for primary, 0 for secondary interface */ return (readword == readback) ? 1 : 0; } static int configure_21555_CSRs(struct pci_dev *pdev) { int result; unsigned int value; /* * The IXP CSR space is mapped from location * 0 of PCI address space. */ result = pci_write_config_dword(pdev, DOWNSTREAM_XLAT1, 0x00000000); if (result != PCIBIOS_SUCCESSFUL) { Debug(("21555: Error writing translation CSR for Downstream 1.\n")); return -EIO; } result = pci_read_config_dword(pdev, DOWNSTREAM_XLAT1, &value); if (result != PCIBIOS_SUCCESSFUL) { Debug(("21555: Error reading translation CSR for Downstream 1.\n")); return -EIO; } else Debug(("21555: Translation Base for Downstream 1 is now 0x%x\n", value)); return result; } static int host_21555_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent) { int result = -ENODEV; int primary; primary = check_21555_interface(pdev); if (unlikely(primary < 0)) goto err_out; Debug(("21555: %s interface\n", primary ? "host" : "local")); if (unlikely(primary == 0)) { printk("21555: Uhh! Trying to load this module on the secondary???\n"); goto err_out; } else result = 0; pcidev_21555 = pdev; if (check_mem_region(pci_resource_start(pdev, 2), 1024*1024)) { Debug(("21555: BAR 2 already mapped.\n")); result = -EBUSY; goto err_out1; } else request_mem_region(pci_resource_start(pdev, 2), 1024*1024, "21555 downstream window 1"); cap_csr = ioremap_nocache(pci_resource_start(pdev, 2), 1024*1024); if (cap_csr == NULL) { result = -ENOMEM; goto err_out; } else Debug(("21555: cap_csr at vaddr 0x%x\n", (unsigned int) cap_csr)); if (pci_enable_device(pdev) < 0) { Debug(("21555: Couldn't enable 21555 master.\n")); goto err_out1; } pci_set_master(pdev); /* Smooth sailing so far. Load the configuration registers now. */ result = configure_21555_CSRs(pdev); if (!result) return result; err_out1: if (cap_csr) { iounmap((void *)cap_csr); cap_csr = NULL; } err_out: return result; } static void host_21555_pci_remove(struct pci_dev *pdev) { pci_disable_device(pdev); if (cap_csr) { iounmap((void *) cap_csr); cap_csr = NULL; } if (check_mem_region(pci_resource_start(pdev, 2), 1024*1024)) { release_mem_region(pci_resource_start(pcidev_21555, 2), 1024*1024); } return; } static struct pci_driver host_21555_driver = { name: "host_21555", id_table: bridge_tbl, probe: host_21555_pci_init, remove: host_21555_pci_remove, /* TODO: Enable power management for this driver */ }; static int write_21555(struct file *file, const char *buffer, unsigned long count, void *data) { int i; MOD_INC_USE_COUNT; /* * Take care of user forced resets on ENP * by re-writing config space. */ for(i = 0; i < 256; i++) pci_write_config_byte(pcidev_21555, i, config_space[i]); /* * Reset the IXP. * Pg 332 of Intel IXP2400/2800 Network Processor, * Programmers reference manual (July 2003). */ *((int *)(cap_csr + 0x4a0c)) = (1<<16); MOD_DEC_USE_COUNT; return count; } static struct proc_dir_entry *write_21555_entry; int __init host_21555_init(void) { int result; int i; char value; printk("21555: Loading 21555 driver on the host CPU.\n"); result = pci_module_init(&host_21555_driver); if (!result) { write_21555_entry = create_proc_entry("ntb", 0644, NULL); if (write_21555_entry == NULL) { result = -ENOMEM; goto err_out; } write_21555_entry->owner = THIS_MODULE; write_21555_entry->write_proc = write_21555; } else return result; /* * save config space to handle * resets of the ENP by user. */ for(i = 0; i < 256; i++) { pci_read_config_byte(pcidev_21555, i, &value); config_space[i] = value; } return result; err_out: pci_unregister_driver(&host_21555_driver); return result; } void __exit host_21555_exit(void) { int i; /* * handle cases where the module was * loaded and unloaded after a user * reset of ENP. */ for(i = 0; i < 256; i++) pci_write_config_byte(pcidev_21555, i, config_space[i]); printk("21555: Removing the 21555 driver on the host CPU.\n"); pci_unregister_driver(&host_21555_driver); remove_proc_entry("ntb", NULL); return; } module_init(host_21555_init); module_exit(host_21555_exit); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Intel 21555 bridge driver used to reset Radisys board from host"); /* * assmuming /usr/src/linux -> <actual source tree of currently running kernel> * Compile with * gcc -Wall -DMODULE -D__KERNEL__ -I /usr/src/linux/include -c -O2 hostb.c */

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need some header files
by Rajas Raut 15 Mar '04

15 Mar '04

Dear All I need three header files of IXP 1200 SDK . ixp.h, CSR.h and buffer.h if anybody can send it to me ...I will be highly thankful.. I need these files for a project of mine. Regards Rajas Raut www.rajasraut.cjb.net ----------------------------------------- (on isc) ________________________________________________________________________________ Mail Scanned: TREND InterScan VirusWall Information Superhighway Centre, IIT Roorkee ---------------------------------------------------------

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spread code over multiple microengines (using the ACE model)
by Tim Stevens 15 Mar '04

15 Mar '04

Hi all, Can anyone on this list provide me some details on how to spread code over several microengines (e.g. one ingress ACE on ME1, one L3 component on ME2, one egress component on ME3)? Until now, we have done everything on 2 microengines (when using the microACE framework, as presented in the tutorial), but distributing the load over more MEs seems more appropriate in the future. The configuration file (ixsys.config) requires one chooses between ingress or egress for each ace, but this is not suitable for the L3 component on ME2 (previous paragraph). Any ideas? Any help would be greatly appreciated! Kind regards, Tim

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RE: [ixp1200] 1K or 2K instruction cache?
by Tim Stevens 15 Mar '04

15 Mar '04

Hi Jim, And can you tell me how we can do that? Or how we tell the compiler to branch to the second store? Thanks! Regards, Tim At 17:33 15/03/2004, you wrote: >If you have the version of 1200 that contains 2k of instruction memory >you can have upto 2k of instructions. But the instructions are stored >in two separate 1k areas and you need to branch between the two areas. > >-----Original Message----- >From: Tim Stevens [mailto:tim.stevens@intec.ugent.be] >Sent: Monday, March 15, 2004 11:28 AM >To: ixp1200(a)lists.cs.princeton.edu >Subject: [ixp1200] 1K or 2K instruction cache? > > >Hi all, > >We use a RadiSys ENP-2505 board and encounter a problem concerning the >microengine instruction cache size. >Each time we compile the code, the compiler complains that it doesn't fit >into the instruction memory (total size between 1K and 2K instructions), >while our RadiSys documentation states that we have a 2K instruction >cache... >Does this mean that we have to set a specific compiler flag, or is one >instruction larger than one unit in the instruction cache (meaning that a >2K cache can only hold about 1K instructions)? > >Any help would be appreciated. > >Kind regards, > >Tim > >_______________________________________________ >ixp1200 mailing list >ixp1200(a)lists.cs.princeton.edu >https://lists.cs.princeton.edu/mailman/listinfo/ixp1200 > > > - - - - - - - Appended by Scientific-Atlanta, Inc. - - - - - - - >This e-mail and any attachments may contain information which is >confidential, proprietary, privileged or otherwise protected by law. The >information is solely intended for the named addressee (or a person >responsible for delivering it to the addressee). If you are not the >intended recipient of this message, you are not authorized to read, print, >retain, copy or disseminate this message or any part of it. If you have >received this e-mail in error, please notify the sender immediately by >return e-mail and delete it from your computer. > >_______________________________________________ >ixp1200 mailing list >ixp1200(a)lists.cs.princeton.edu >https://lists.cs.princeton.edu/mailman/listinfo/ixp1200

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RE: [ixp1200] need some header files
by Johnson, Erik J 15 Mar '04

15 Mar '04

ixp.h should be in ixp1200\uEngineC\include. I don't know of a CSR.h or buffer.h in the IXA SDK 2.0. However, files with the same name are included with the IXP1200 Programming book CD-ROM. CSR.h is in the Common\ directory and buffer.h is in many of the ChapterXX\ directories. I'll send these separate to you. erik ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Erik J. Johnson Intel Research & Development erik.j.johnson(a)intel.com NOT SPEAKING FOR INTEL ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----Original Message----- From: ixp1200-bounces(a)lists.cs.princeton.edu [mailto:ixp1200-bounces@lists.cs.princeton.edu] On Behalf Of Rajas Raut Sent: Monday, March 15, 2004 6:01 PM To: ixp1200(a)lists.cs.princeton.edu Subject: [ixp1200] need some header files Dear All I need three header files of IXP 1200 SDK . ixp.h, CSR.h and buffer.h if anybody can send it to me ...I will be highly thankful.. I need these files for a project of mine. Regards Rajas Raut www.rajasraut.cjb.net

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RE: [ixp1200] 1K or 2K instruction cache?
by Johnson, Erik J 15 Mar '04

15 Mar '04

Yes, for the assembler one must insert the unconditional branches across the 1K boundary. For microC, I believe the compiler will only insert such branches at function boundaries. So, if you are forcing all of your functions to be inlined, main() may become larger than 1K instructions. I have had this problem before and the simple fix is to not inline one or more routines to allow the compiler to place them in a different segment from the "scope" of main(). erik -----Original Message----- From: ixp1200-bounces(a)lists.cs.princeton.edu [mailto:ixp1200-bounces@lists.cs.princeton.edu] On Behalf Of Elsenbeck, Jim Sent: Monday, March 15, 2004 8:34 AM To: 'IXP1200 Developer's List' Subject: RE: [ixp1200] 1K or 2K instruction cache? If you have the version of 1200 that contains 2k of instruction memory you can have upto 2k of instructions. But the instructions are stored in two separate 1k areas and you need to branch between the two areas. -----Original Message----- From: Tim Stevens [mailto:tim.stevens@intec.ugent.be] Sent: Monday, March 15, 2004 11:28 AM To: ixp1200(a)lists.cs.princeton.edu Subject: [ixp1200] 1K or 2K instruction cache? Hi all, We use a RadiSys ENP-2505 board and encounter a problem concerning the microengine instruction cache size. Each time we compile the code, the compiler complains that it doesn't fit into the instruction memory (total size between 1K and 2K instructions), while our RadiSys documentation states that we have a 2K instruction cache... Does this mean that we have to set a specific compiler flag, or is one instruction larger than one unit in the instruction cache (meaning that a 2K cache can only hold about 1K instructions)? Any help would be appreciated. Kind regards, Tim _______________________________________________ ixp1200 mailing list ixp1200(a)lists.cs.princeton.edu https://lists.cs.princeton.edu/mailman/listinfo/ixp1200 - - - - - - - Appended by Scientific-Atlanta, Inc. - - - - - - - This e-mail and any attachments may contain information which is confidential, proprietary, privileged or otherwise protected by law. The information is solely intended for the named addressee (or a person responsible for delivering it to the addressee). If you are not the intended recipient of this message, you are not authorized to read, print, retain, copy or disseminate this message or any part of it. If you have received this e-mail in error, please notify the sender immediately by return e-mail and delete it from your computer. _______________________________________________ ixp1200 mailing list ixp1200(a)lists.cs.princeton.edu https://lists.cs.princeton.edu/mailman/listinfo/ixp1200

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RE: [ixp1200] 1K or 2K instruction cache?
by Elsenbeck, Jim 15 Mar '04

15 Mar '04

If you have the version of 1200 that contains 2k of instruction memory you can have upto 2k of instructions. But the instructions are stored in two separate 1k areas and you need to branch between the two areas. -----Original Message----- From: Tim Stevens [mailto:tim.stevens@intec.ugent.be] Sent: Monday, March 15, 2004 11:28 AM To: ixp1200(a)lists.cs.princeton.edu Subject: [ixp1200] 1K or 2K instruction cache? Hi all, We use a RadiSys ENP-2505 board and encounter a problem concerning the microengine instruction cache size. Each time we compile the code, the compiler complains that it doesn't fit into the instruction memory (total size between 1K and 2K instructions), while our RadiSys documentation states that we have a 2K instruction cache... Does this mean that we have to set a specific compiler flag, or is one instruction larger than one unit in the instruction cache (meaning that a 2K cache can only hold about 1K instructions)? Any help would be appreciated. Kind regards, Tim _______________________________________________ ixp1200 mailing list ixp1200(a)lists.cs.princeton.edu https://lists.cs.princeton.edu/mailman/listinfo/ixp1200 - - - - - - - Appended by Scientific-Atlanta, Inc. - - - - - - - This e-mail and any attachments may contain information which is confidential, proprietary, privileged or otherwise protected by law. The information is solely intended for the named addressee (or a person responsible for delivering it to the addressee). If you are not the intended recipient of this message, you are not authorized to read, print, retain, copy or disseminate this message or any part of it. If you have received this e-mail in error, please notify the sender immediately by return e-mail and delete it from your computer.

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1K or 2K instruction cache?
by Tim Stevens 15 Mar '04

15 Mar '04

Hi all, We use a RadiSys ENP-2505 board and encounter a problem concerning the microengine instruction cache size. Each time we compile the code, the compiler complains that it doesn't fit into the instruction memory (total size between 1K and 2K instructions), while our RadiSys documentation states that we have a 2K instruction cache... Does this mean that we have to set a specific compiler flag, or is one instruction larger than one unit in the instruction cache (meaning that a 2K cache can only hold about 1K instructions)? Any help would be appreciated. Kind regards, Tim

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Flash problem with ENP-2505
by vinay kini 15 Mar '04

15 Mar '04

Hi, I'm a beginner using the ENP-2505, and have got myself into a strange (and probably serious) problem. I experimented with the reflash and reprogram commands in the System Monitor, and one of them stopped midway. Now my flash is corrupt. I cannot even load the System Monitor, Cygmon or VxWorks. When I try, there is no response at all from the serial interface, everything just stops (and yeah, the LEDs also stop blinking, which indicates a flash problem). Only the boot manager runs. If I start the Flash Utility, and run FUtil.exe on Windows NT, FUtil terminates saying "No recognized flash types found on board: C5 C5 C5 C5". Please help! Is there a way to reprogram the whole flash? I believe the Flash Utility on the board is still working (along with the Boot Manager). Thanks, Vinay

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A dumb question
by Sanjay Kumar 14 Mar '04

14 Mar '04

Hi Folks, enp2611 (IXP2400) board runs in MPHY-4 mode so it can support up to 4 ports. but enp2611 has only 3 gigabit ports. does this mean the 4th port on enp2611 is unused? or am I missing something? Thanks, Sanjay ---------------------------------- http://www.cc.gatech.edu/~ksanjay/

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New list for IXP2400/IXP2800
by Scott Karlin 10 Mar '04

10 Mar '04

This is to announce the creation of a new list specifically for the discussion on the topic of the IXP2400 and IXP2800 network processors. You may subscribe here: https://lists.cs.princeton.edu/mailman/listinfo/ixp2xxx Scott

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Embedded Debugging Utilty
by Prakhyath Makam 09 Mar '04

09 Mar '04

I have configured the ixp1200eb to run in diagnostics mode through hardware jumper settings as well as through the use of BootMgr, but i dont see any EDU diagnostic message display as given in the fig2-2, section 2.4.1 of ixp1200 eval system user guide manual. Moreover , the jumper settings are all set to "factory settings" itself. Am i missing anything here? Please help. Thanking you inanticipation, Prakhyath Makam.

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RE: [ixp1200] Doubt reg. Floating Point Operations support in IXP 1200
by David Mentre 09 Mar '04

09 Mar '04

Hello, > From: romit dasgupta [mailto:romit@myrealbox.com] > Sent: Tuesday, March 09, 2004 6:30 AM [ about doing floating point computations on IXP1200 core ] > If you are talking about userland, then libm is your friend. > If you are > talking about kernel space > then you may compile your kernel with CONFIG_FPE_NWFPE or > CONFIG_FPE_FASTFPE. Romit, I think you have been confused by the fact the CONFIG_FPE_NWFPE and CONFIG_FPE_FASTFPE are kernel options. In fact, once enabled, they provide floating point emulation for *user* application. BTW, if you want fast floating point computations, it appears that there is a patch floating around (no pun intended) for gcc that implements floating point emulation at the compilation toolchain level. According to linux-arm developers, it is much faster than kernel level emulation. However, this patch requires to recompile all the libraries, including the glibc. On 2004-03-08, in an email entitled "SoftFloat Benchmarks" on arm-linux mailing list, Eric BENARD / Free [ebenard(a)free.fr] has posted a comparison of the different solutions: --- email included --- I've run some benchs in order to compare FP solutions on an IXP425 (rev0) running at 533 MHz with Linux 2.4.21-rmk1-ds3 (with NWFPE patches from the arm-kernel ML). Test softwares are : nbench v2 and flops 2.0 Test compilers are : - gcc 3.3.3 + glibc 2.3.2 => using kernel emulation NWFPE or FFPE - gcc 3.3.3 + Nico's patches + glibc 2.3.2 Compiler options are : -O3 -fomit-frame-pointer -mcpu=xscale -mtune=xscale -mbig-endian -static Results : *** nbench, Floating Point Index (vs P90 / vs K6/233) : NWFPE : 0.028 / 0.015 FFPE : 0.062 / 0.031 = NWFPE * 2.2 NICO : 0.260 / 0.144 = NWFPE * 9.3 *** flops, mean of the 4 MFLOPS values returned by the test : NWFPE : 0.52 FFPE : 1.89 = NWFPE * 3.63 NICO : 3.91 = NWFPE * 7.52 --- end of email included --- If you want fast floating point anyway, you'd better do fix point computations on integers. It is not allowed by linux kernel developpers to do floating point computations in the kernel. Sharmila, if you want more information on floating point and arm, look at arm-linux mailing list archive. This has been discussed numerous times. Yours, david -- David Mentré <mentre(a)tcl.ite.mee.com> - Research engineer (Ph.D.) Mitsubishi Electric ITE-TCL / European Telecommunication Research Lab Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 http://www.mitsubishi-electric-itce.fr

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RE: [ixp1200] Doubt reg. Floating Point Operations support in IXP 1200
by David Mentre 09 Mar '04

09 Mar '04

Hello Romit, > From: romit dasgupta [mailto:romit@myrealbox.com] > Sent: Tuesday, March 09, 2004 10:04 AM > Thanks for your mail. Once I did a division > operation in the kernel and I got an error given by the assembler. I > enabled CONFIG_FPE_FASTFPE and the error vanished. Oh, I see. The CONFIG_FPE_FASTFPE option adds an handler on FP exception, so it also works within the kernel. I was wrong for that. > You are > right we are > not supposed to do FP operations in Kernel but my > understanding is that, > if we do really need FP operations in kernel we have to > explicitly save > the FP context. Correct me if I am wrong. I think you are right. However it might raise subtle bugs if you fail to save/restore the FP context at one scheduling point. > By the way, if we dont enable CONFIG_FPE_FASTFPE, cant we > still use libm > from userspace? I don't know. Yours, d. -- David Mentré <mentre(a)tcl.ite.mee.com> - Research engineer (Ph.D.) Mitsubishi Electric ITE-TCL / European Telecommunication Research Lab Phone: +33 2 23 45 58 29 / Fax: +33 2 23 45 58 59 http://www.mitsubishi-electric-itce.fr

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Doubt reg. Floating Point Operations support in IXP1200
by sharmila radhakrishnan 09 Mar '04

09 Mar '04

Hello All, I have a doubt.IXP1200 doesnot support floating point operations.Is their any way in which computations involving floating point operations can be done.I would be very much thankful if you'll could help me out with this.Thanx in advance. Regards, Sharmila Yahoo! India Insurance Special: Be informed on the best policies, services, tools and more.

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Time Is Running Out. IXA University Program IXP425 Student Design Competition
by Schuetze, Joel D 08 Mar '04

08 Mar '04

Greetings, Just a quick note to remind you that time is running out to get your entries submitted for the IXA University Program IXP425 Student Design Competition. Entries must be received by March 26th. The Intel IXA University Program Student Design competition will allow undergraduate and graduate university students from U.S. Universities to present innovative work based on the Intel(r) IXA architecture, specifically the IXP425 network processor. We have a web-based application process available through the IXAEDU.com website and all entries will be reviewed by an Intel panel of experts. The best qualified selected entries will be awarded grants and IXP425 development kits for the proposed projects. After the selected projects have been completed and submitted for judging, the top two (2) projects will be selected to receive an award presented at the Fall 2004 Intel Developer Forum (IDF). Please note that this competition is available for students enrolled at US Universities only. For complete information please visit http://ixaedu.com/news/DesignCompetition. IXA University Program Intel Corporation

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Reg TRIES
by dveluchamy＠vsnl.net 06 Mar '04

06 Mar '04

Hi all, Does Intel provide any library for working with tries? I find there is a mention of TRIE5 & TRIE8, but couldn't anything more in the docs. Thanx in advance. D.Veluchamy

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RE: [ixp1200] IXP1200 or IXF440 maximum MTU
by Botham, Mick 04 Mar '04

04 Mar '04

Tim, The IXF440 will process packets upto the size programmed into the 'Maximium Packet Size' register, although this accepts values upto 15 bits, you should limit this to Jumbo packet length. Rgds Mick -----Original Message----- From: ixp1200-bounces(a)lists.cs.princeton.edu [mailto:ixp1200-bounces@lists.cs.princeton.edu] On Behalf Of Tim Stevens Sent: 04 March 2004 15:27 To: ixp1200(a)lists.cs.princeton.edu Subject: [ixp1200] IXP1200 or IXF440 maximum MTU Hi, Can anyone tell me whether the IXP1200 boards (ours=ENP-2505) are capable of processing ethernet frames larger than 1500 bytes? Or is the IXF440 the limiting factor? I'm asking this because it might be practical to implement VLAN tagging 802.1Q (this adds 4 bytes to an ethernet frame) or other layer 2 features. Thanks. Kind regards, Tim _______________________________________________ ixp1200 mailing list ixp1200(a)lists.cs.princeton.edu https://lists.cs.princeton.edu/mailman/listinfo/ixp1200

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